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1. (WO2018142970) TRANSISTOR AND MANUFACTURING METHOD
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Pub. No.: WO/2018/142970 International Application No.: PCT/JP2018/001587
Publication Date: 09.08.2018 International Filing Date: 19.01.2018
IPC:
H01L 21/336 (2006.01) ,H01L 21/265 (2006.01) ,H01L 27/146 (2006.01) ,H01L 29/78 (2006.01) ,H04N 5/374 (2011.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
26
Bombardment with wave or particle radiation
263
with high-energy radiation
265
producing ion implantation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
14
including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
144
Devices controlled by radiation
146
Imager structures
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
N
PICTORIAL COMMUNICATION, e.g. TELEVISION
5
Details of television systems
30
Transforming light or analogous information into electric information
335
using solid-state image sensors [SSIS]
369
SSIS architecture; Circuitry associated therewith
374
Addressed sensors, e.g. MOS or CMOS sensors
Applicants:
ソニーセミコンダクタソリューションズ株式会社 SONY SEMICONDUCTOR SOLUTIONS CORPORATION [JP/JP]; 神奈川県厚木市旭町四丁目14番1号 4-14-1, Asahi-cho, Atsugi-shi, Kanagawa 2430014, JP
Inventors:
澤田 憲 SAWADA Ken; JP
本庄 亮子 HONJO Akiko; JP
Agent:
西川 孝 NISHIKAWA Takashi; JP
稲本 義雄 INAMOTO Yoshio; JP
Priority Data:
2017-01816103.02.2017JP
2017-21001231.10.2017JP
Title (EN) TRANSISTOR AND MANUFACTURING METHOD
(FR) TRANSISTOR ET PROCÉDÉ DE FABRICATION
(JA) トランジスタ、製造方法
Abstract:
(EN) The present technology relates to a transistor enabling to reduce noise, and a manufacturing method. This transistor is provided with: a gate electrode formed on a semiconductor substrate; a source region formed as a part of a semiconductor substrate surface such that the source region extends from the gate electrode; and a drain region formed as a part of the semiconductor substrate surface such that there is no portion in contact with the gate electrode, said drain region being at a position facing the source region. The source region and the drain region are asymmetrical to each other. The drain region is formed at a position deeper than the source region. At a gate end of the gate electrode, the drain region is formed at a position separated from the surface of the semiconductor substrate. The present technology can be applied to, for instance, amplification transistors.
(FR) La présente invention concerne un transistor permettant de réduire le bruit, et un procédé de fabrication. Ce transistor comprend : une électrode de grille formée sur un substrat semiconducteur; une région de source formée en tant que partie d'une surface de substrat semiconducteur de telle sorte que la région de source s'étend à partir de l'électrode de grille; et une région de drain formée en tant que partie de la surface de substrat semiconducteur de telle sorte qu'il n'y a pas de partie en contact avec l'électrode de grille, ladite région de drain étant dans une position faisant face à la région de source. La région de source et la région de drain sont asymétriques l'une par rapport à l'autre. La région de drain est formée à une position plus profonde que la région de source. Au niveau d'une extrémité de grille de l'électrode de grille, la région de drain est formée à une position séparée de la surface du substrat semiconducteur. La présente invention peut être appliquée, par exemple, à des transistors d'amplification.
(JA) 本技術は、ノイズを低減させることができるようにするトランジスタ、製造方法に関する。 半導体基板上に形成されたゲート電極と、ゲート電極から延在するように半導体基板表面に形成されたソース領域と、ソース領域と対向する位置に、ゲート電極に接触する部分がないように半導体基板表面に形成されたドレイン領域とを備える。ソース領域とドレイン領域は、非対称である。ドレイン領域は、ソース領域よりも深い位置に形成されている。ゲート電極のゲート端において、ドレイン領域は、半導体基板の表面から離れた位置に形成されている。本技術は、例えば、増幅トランジスタに適用できる。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)