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|1. (WO2018142478) SEMICONDUCTOR MEMORY DEVICE|
|Applicants:||ZENTEL JAPAN CORPORATION
|Title:||SEMICONDUCTOR MEMORY DEVICE|
A plurality of memory cells (11) are arranged along a plurality of bit lines (13) and a plurality of word lines (15). A sense amplifier (14) is connected to each of the bit lines (13). Arranged along each bit line (13) are at least four memory cells (11) including first to fourth memory cells (11) that are either connected to or disconnected from one of the bit lines (13) by means of first to fourth switching elements (12) according to an active or inactive state of first to fourth word lines (15). The first memory cell (11) stores a first bit value, the second memory cell (11) stores a second bit value, and the third and fourth memory cells (11) each store a third bit value. A memory cell array control circuit (22) activates and then deactivates the third and fourth word lines (15), subsequently activates the first and second word lines (15), and then activates the sense amplifier (14).