Search International and National Patent Collections

1. (WO2018141663) CIRCUIT FOR GENERATING A SAMPLING SIGNAL FOR A UART INTERFACE, AND UART INTERFACE

Pub. No.:    WO/2018/141663    International Application No.:    PCT/EP2018/052036
Publication Date: Fri Aug 10 01:59:59 CEST 2018 International Filing Date: Tue Jan 30 00:59:59 CET 2018
IPC: G06F 1/08
Applicants: LENZE AUTOMATION GMBH
Inventors: DÜSTERBERG, Dirk
Title: CIRCUIT FOR GENERATING A SAMPLING SIGNAL FOR A UART INTERFACE, AND UART INTERFACE
Abstract:
A circuit (1) for generating a sampling signal (AS) for a UART interface (20), wherein the circuit (1) has – an input port (2) configured to receive a peripheral clock (PT), – an output port (3) configured to output the sampling signal (AS), – a bit rate memory (4) configured to store a value corresponding to a desired bit rate of the UART interface, – a peripheral clock memory (5) configured to store a value corresponding to a frequency of the peripheral clock, – a sum memory (6) configured to store a summed value, and – a computation unit (7) configured to – compare a comparison value (VW), which is dependent on the summed value stored in the sum memory (6), with a threshold value (SW), which is dependent on the value stored in the peripheral clock memory (5), – take the result of the comparison as a basis for generating the sampling signal (AS) at a first level or a second level, and – use the timing of the peripheral clock (PT), and take the result of the comparison as a basis, for either altering the summed value stored in the sum memory (6) by the value stored in the bit rate memory (4) or altering the summed value stored in the sum memory (6) by a value that is dependent on the value stored in the peripheral clock memory (5).