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1. (WO2018140948) INTEGRATED STRUCTURES, NAND MEMORY ARRAYS, AND METHODS OF FORMING INTEGRATED STRUCTURES

Pub. No.:    WO/2018/140948    International Application No.:    PCT/US2018/015962
Publication Date: Fri Aug 03 01:59:59 CEST 2018 International Filing Date: Wed Jan 31 00:59:59 CET 2018
IPC: H01L 27/11556
H01L 27/11519
H01L 27/11524
H01L 27/11529
Applicants: MICRON TECHNOLOGY, INC.
Inventors: HOPKINS, John, D.
DAYCOCK, David
Title: INTEGRATED STRUCTURES, NAND MEMORY ARRAYS, AND METHODS OF FORMING INTEGRATED STRUCTURES
Abstract:
Some embodiments include an integrated structure having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include primary regions of a first vertical thickness, and terminal projections of a second vertical thickness which is greater than the first vertical thickness. Charge-blocking material is adjacent the terminal projections. Charge-storage material is adjacent the charge- blocking material. Gate-dielectric material is adjacent the charge-storage material. Channel material is adjacent the gate-dielectric material. Some embodiments include NAND memory arrays. Some embodiments include methods of forming integrated structures.