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1. (WO2018140104) METHOD AND SYSTEM FOR DEFECT PREDICTION OF INTEGRATED CIRCUITS
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2018/140104 International Application No.: PCT/US2017/059027
Publication Date: 02.08.2018 International Filing Date: 30.10.2017
IPC:
G01N 21/88 (2006.01) ,G01N 21/95 (2006.01) ,G01N 21/01 (2006.01)
G PHYSICS
01
MEASURING; TESTING
N
INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
21
Investigating or analysing materials by the use of optical means, i.e. using infra-red, visible, or ultra-violet light
84
Systems specially adapted for particular applications
88
Investigating the presence of flaws, defects or contamination
G PHYSICS
01
MEASURING; TESTING
N
INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
21
Investigating or analysing materials by the use of optical means, i.e. using infra-red, visible, or ultra-violet light
84
Systems specially adapted for particular applications
88
Investigating the presence of flaws, defects or contamination
95
characterised by the material or shape of the object to be examined
G PHYSICS
01
MEASURING; TESTING
N
INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
21
Investigating or analysing materials by the use of optical means, i.e. using infra-red, visible, or ultra-violet light
01
Arrangements or apparatus for facilitating the optical investigation
Applicants:
DONGFANG JINGYUAN ELECTRON LIMITED [CN/CN]; 156 4th Jinghai Road, Building 12 Beijing Economic Development District Beijing, CN 10076, CN
Inventors:
YU, Zongchang; US
LIN, Jie; US
ZHANG, Zhaoli; US
Agent:
XIAO, Lin; US
KNIGHT, Michelle L.; US
Priority Data:
15/419,64330.01.2017US
Title (EN) METHOD AND SYSTEM FOR DEFECT PREDICTION OF INTEGRATED CIRCUITS
(FR) PROCÉDÉ ET SYSTÈME DE PRÉDICTION DE DÉFAUTS DE CIRCUITS INTÉGRÉS
Abstract:
(EN) Methods and systems for defect prediction are provided. The method includes receiving feature data of an integrated circuit (IC) and process condition data of a production process associated with the IC, and determining a care area associated with the IC using the feature data, the process condition data, and a defect prediction technique, wherein the care area includes a potential defect and is inspected by a high-resolution inspection system. Based on the provided methods and systems, care areas can be generated incorporating actual process conditions when the inspected IC is being manufactured, and fast and high-resolution IC defect inspection systems can be implemented.
(FR) L’invention concerne des procédés et des systèmes de prédiction de défauts. Le procédé consiste à recevoir des données d’attributs d’un circuit intégré (CI) et des données de conditions de processus d’un processus de production associé au CI, et à déterminer une zone de soin associée au CI au moyen des données d’attributs, des données de conditions de processus, et d’une technique de prédiction de défauts, la zone de soin incluant un défaut potentiel et étant inspectée par un système d’inspection à haute résolution. Sur la base des procédés et des systèmes selon l’invention, des zones de soin peuvent être générées en incorporant des conditions de processus réelles lorsque le CI inspecté est fabriqué, et des systèmes d’inspection de défauts de CI rapides et à haute résolution peuvent être réalisés.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)