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1. (WO2018139265) PROCESSOR, INFORMATION PROCESSING DEVICE, AND PROCESSOR OPERATION METHOD

Pub. No.:    WO/2018/139265    International Application No.:    PCT/JP2018/000987
Publication Date: Fri Aug 03 01:59:59 CEST 2018 International Filing Date: Wed Jan 17 00:59:59 CET 2018
IPC: G06F 15/16
G06F 9/38
G06F 15/80
G06N 3/10
G06T 1/20
Applicants: FUJITSU LIMITED
富士通株式会社
Inventors: YODA, Katsuhiro
依田 勝洋
TOMONO, Mitsuru
伴野 充
NOTSU, Takahiro
野津 隆弘
Title: PROCESSOR, INFORMATION PROCESSING DEVICE, AND PROCESSOR OPERATION METHOD
Abstract:
[Problem] To efficiently perform reading processing of image data by a core within a processor. [Solution] A processor comprising: a plurality of computing cores (CORE); a plurality of pieces of individual memory (IMEM) accessed from the computing cores; a plurality of pieces of shared memory (SMEM) provided to each of the plurality of computing cores; a plurality of memory control circuits (MAU) provided between each of the plurality of computing cores and the plurality of pieces of individual memory; a plurality of selectors (SL) provided to each of the plurality of pieces of shared memory; and a control core (C_CORE) for controlling the plurality of computing cores. For each of the plurality of memory control circuits, the control core sets the transfer source addresses of shared memory and individual memory in which transfer data to be transferred between the plurality of computing cores is stored and the transfer destination address of shared memory to which the transfer data is to be transferred, and when transfer select information is set in the plurality of selectors and the addresses of the read requests of a computing core (CORE0) to which each of the plurality of memory control circuits belongs match the transfer source addresses, each of the plurality of memory control circuits transfers the transfer data for the read requests to the transfer destination address via the selectors in which the transfer select information is set. When the control core sets read select information in each of the plurality of selectors, read data is read for each of the plurality of pieces of shared memory from a computer core to which the shared memory belongs and from one of first adjacent cores via the selectors in which the read select information is set.