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1. (WO2018139188) SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SAME, SOLID-STATE IMAGE PICKUP ELEMENT, AND ELECTRONIC APPARATUS
Latest bibliographic data on file with the International Bureau    Submit observation
Pub. No.: WO/2018/139188 International Application No.: PCT/JP2018/000232
Publication Date: 02.08.2018 International Filing Date: 10.01.2018
IPC:
H01L 27/146 (2006.01) ,H01L 21/3205 (2006.01) ,H01L 21/768 (2006.01) ,H01L 21/822 (2006.01) ,H01L 23/522 (2006.01) ,H01L 27/04 (2006.01) ,H04N 5/369 (2011.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
14
including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
144
Devices controlled by radiation
146
Imager structures
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
N
PICTORIAL COMMUNICATION, e.g. TELEVISION
5
Details of television systems
30
Transforming light or analogous information into electric information
335
using solid-state image sensors [SSIS]
369
SSIS architecture; Circuitry associated therewith
Applicants:
ソニーセミコンダクタソリューションズ株式会社 SONY SEMICONDUCTOR SOLUTIONS CORPORATION [JP/JP]; 神奈川県厚木市旭町四丁目１４番１号 4-14-1, Asahi-cho, Atsugi-shi, Kanagawa 2430014, JP
Inventors:
高橋　洋 TAKAHASHI Hiroshi; JP
Agent:
西川　孝 NISHIKAWA Takashi; JP
稲本　義雄 INAMOTO Yoshio; JP
Priority Data:
2017-01005324.01.2017JP
Title (EN) SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SAME, SOLID-STATE IMAGE PICKUP ELEMENT, AND ELECTRONIC APPARATUS
(FR) DISPOSITIF À SEMICONDUCTEUR, SON PROCÉDÉ DE FABRICATION, ÉLÉMENT DE CAPTURE D'IMAGE À SEMICONDUCTEUR ET DISPOSITIF ÉLECTRONIQUE
(JA) 半導体装置および製造方法、固体撮像素子、並びに電子機器
Abstract:
(EN) The present technology relates to: a semiconductor device enabling to suppress breakage of a side wall insulating film due to charge damage, and to suppress a short-circuit that could have been occurred between a semiconductor substrate and a through electrode; a method for manufacturing the semiconductor device; a solid-state image pickup element; and an electronic apparatus. The semiconductor device according to one aspect of the present technology is provided with: a first semiconductor substrate, in which a predetermined circuit is formed; a second semiconductor substrate bonded to the first semiconductor substrate; and a through electrode that electrically connects the first semiconductor substrate and the second semiconductor substrate to each other. The through electrode is formed by opening a through hole by penetrating a protection diode structure formed in the first semiconductor substrate, depositing an insulating film on the side wall of the through hole, and applying an electrode material to the inner side of the through hole on which the insulating film is deposited. This technology can be applied to, for instance, CMOS image sensors.
(FR) La présente invention concerne : un dispositif à semiconducteur permettant d'empêcher la rupture d'un film d'isolation de paroi latérale en raison d'un endommagement de charge, et pour empêcher un court-circuit qui pourrait avoir été produit entre un substrat semiconducteur et une électrode traversante; un procédé de fabrication du dispositif à semiconducteur; un élément de capture d'image à semiconducteur; et un appareil électronique. Selon un aspect de la présente invention, le dispositif à semiconducteur comprend : un premier substrat semiconducteur, sur lequel est formé un circuit prédéterminé; un second substrat semiconducteur lié au premier substrat semiconducteur; et une électrode traversante qui connecte électriquement le premier substrat semiconducteur et le second substrat semiconducteur l'un à l'autre. L'électrode traversante est formée par ouverture d'un trou traversant par pénétration d'une structure de diode de protection formée sur le premier substrat semiconducteur, déposer un film d'isolation sur la paroi latérale du trou traversant, et appliquer un matériau d'électrode sur le côté interne du trou traversant sur lequel le film isolant est déposé. La présente invention peut être appliquée, par exemple, à des capteurs d'image CMOS.
(JA) 本技術は、チャージダメージによる側壁絶縁膜の破壊を抑えて半導体基板と貫通電極間に生じ得ていた短絡を抑止できるようにする半導体装置および製造方法、固体撮像素子、並びに電子機器に関する。 本技術の一側面である半導体装置は、所定の回路が形成されている第１半導体基板と、前記第１半導体基板と貼り合わされた第２半導体基板と、前記第１半導体基板と前記第２半導体基板とを電気的に接続する貫通電極とを備え、前記貫通電極は、前記第１半導体基板内に形成されている保護ダイオード構造を貫いてスルーホールが開口され、前記スルーホールの側壁に絶縁膜が堆積され、前記絶縁膜が堆積されている前記スルーホール内側に電極材が充填されて形成されている。本技術は、例えば、CMOSイメージセンサに適用できる。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)