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1. (WO2018139027) SEMICONDUCTOR DEVICE
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Pub. No.: WO/2018/139027 International Application No.: PCT/JP2017/042179
Publication Date: 02.08.2018 International Filing Date: 24.11.2017
IPC:
H01L 29/06 (2006.01) ,H01L 29/41 (2006.01) ,H01L 29/47 (2006.01) ,H01L 29/872 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
43
characterised by the materials of which they are formed
47
Schottky barrier electrodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
86
controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
861
Diodes
872
Schottky diodes
Applicants:
富士電機株式会社 FUJI ELECTRIC CO., LTD. [JP/JP]; 神奈川県川崎市川崎区田辺新田1番1号 1-1, Tanabeshinden, Kawasaki-ku, Kawasaki-shi, Kanagawa 2109530, JP
Inventors:
尾崎 大輔 OZAKI Daisuke; JP
河野 涼一 KAWANO Ryouichi; JP
Agent:
龍華国際特許業務法人 RYUKA IP LAW FIRM; 東京都新宿区西新宿1-6-1 新宿エルタワー22階 22F, Shinjuku L Tower, 1-6-1, Nishi-Shinjuku, Shinjuku-ku, Tokyo 1631522, JP
Priority Data:
2017-01170425.01.2017JP
Title (EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR
(JA) 半導体装置
Abstract:
(EN) Provided is a semiconductor device comprising an active portion and a terminal structure portion. The active portion is disposed on a semiconductor substrate. The terminal structure portion is disposed at a terminal on an upper surface side of the semiconductor substrate to relax an electric field at the terminal. An electric field distribution on the upper surface side of the terminal structure portion may be such that, when a rated voltage is applied, the electric field at an end on the active portion is smaller than a maximum value of the electric field distribution on the upper surface side. The electric field distribution in the terminal structure portion may have a maximum peak of electric field on an edge side opposite the active portion rather than at the center of the terminal structure portion.
(FR) L'invention concerne un dispositif à semi-conducteur comprenant une partie active et une partie structure de borne. La partie active est disposée sur un substrat semi-conducteur. La partie structure de borne se trouve au niveau d'une borne sur un côté de surface supérieure du substrat semi-conducteur de manière à relaxer un champ électrique au niveau de la borne. Une distribution de champ électrique sur le côté de surface supérieure de la partie structure de borne peut être telle que, lors de l'application d'une tension nominale, le champ électrique au niveau d'une extrémité sur la partie active est inférieur à une valeur maximale de la distribution de champ électrique sur le côté de surface supérieure. La distribution de champ électrique dans la partie de structure de borne peut présenter un pic maximal de champ électrique sur un côté de bord opposé à la partie active plutôt qu'au centre de la partie structure de borne.
(JA) 活性部および終端構造部を備える半導体装置を提供する。半導体基板に設けられた活性部と、半導体基板のおもて面側の終端に設けられ、終端の電界を緩和する終端構造部とを備える半導体装置を提供する。終端構造部のおもて面側の電界分布は、定格電圧印加時に、活性部側の端部の電界がおもて面側の電界分布の最大値よりも小さくなっていてよい。また、終端構造部の電界分布は、終端構造部の中心よりも、活性部と反対のエッジ側に電界の最大ピークを有してよい。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)