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1. (WO2018138902) METHOD FOR MANUFACTURING POWER SEMICONDUCTOR DEVICE, AND POWER SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/138902 International Application No.: PCT/JP2017/003137
Publication Date: 02.08.2018 International Filing Date: 30.01.2017
IPC:
H01L 25/07 (2006.01) ,B23K 1/00 (2006.01) ,H01L 21/60 (2006.01) ,H01L 25/18 (2006.01) ,H05K 3/34 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
B PERFORMING OPERATIONS; TRANSPORTING
23
MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
K
SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
1
Soldering, e.g. brazing, or unsoldering
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60
Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18
the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
30
Assembling printed circuits with electric components, e.g. with resistor
32
electrically connecting electric components or wires to printed circuits
34
by soldering
Applicants:
三菱電機株式会社 MITSUBISHI ELECTRIC CORPORATION [JP/JP]; 東京都千代田区丸の内二丁目7番3号 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310, JP
Inventors:
境 紀和 SAKAI, Norikazu; JP
吉田 博 YOSHIDA, Hiroshi; JP
石橋 秀俊 ISHIBASHI, Hidetoshi; JP
浅地 伸洋 ASAJI, Nobuhiro; JP
Agent:
特許業務法人深見特許事務所 FUKAMI PATENT OFFICE, P.C.; 大阪府大阪市北区中之島三丁目2番4号 中之島フェスティバルタワー・ウエスト Nakanoshima Festival Tower West, 2-4, Nakanoshima 3-chome, Kita-ku, Osaka-shi, Osaka 5300005, JP
Priority Data:
Title (EN) METHOD FOR MANUFACTURING POWER SEMICONDUCTOR DEVICE, AND POWER SEMICONDUCTOR DEVICE
(FR) PROCÉDÉ DE FABRICATION D'UN DISPOSITIF À SEMI-CONDUCTEUR DE PUISSANCE ET DISPOSITIF À SEMI-CONDUCTEUR DE PUISSANCE
(JA) パワー半導体装置の製造方法およびパワー半導体装置
Abstract:
(EN) A metal mask (51) is disposed with respect to a copper base plate (3). Patterns of a solder paste (15) are respectively formed on copper plates (5b, 5c, 5d) of the copper base plate (3) by filling a plurality of openings (53) of the metal mask (51) with the solder paste (15). Semiconductor elements (9, 11) and a conductive component (13) are placed on the patterns of the solder paste (15). A metal mask (55) is disposed with respect to the copper base plate (3). Then, patterns of a solder paste (17), said patterns covering the semiconductor elements (9, 11) and the conductive component (13), are formed by filling a plurality of openings (57) of the metal mask (55) with the solder paste (17). A large-capacity relay substrate (21) is disposed such that the large-capacity relay substrate is in contact with the corresponding patterns of the solder paste (17). A power semiconductor device (1) is completed by performing heat treatment under the temperature condition of 200°C or higher.
(FR) Selon l'invention, un masque métallique (51) est disposé par rapport à une plaque de base en cuivre (3). Des motifs d'une pâte à braser (15) sont respectivement formés sur des plaques de cuivre (5b, 5c, 5d) de la plaque de base en cuivre (3) par remplissage d'une pluralité d'ouvertures (53) du masque métallique (51) à l'aide de la pâte à braser (15). Des éléments semi-conducteurs (9, 11) et un composant conducteur (13) sont placés sur les motifs de la pâte à braser (15). Un masque métallique (55) est disposé par rapport à la plaque de base en cuivre (3). Ensuite, des motifs d'une pâte à braser (17) qui recouvrent les éléments semi-conducteurs (9, 11) et le composant conducteur (13) sont formés par remplissage d'une pluralité d'ouvertures (57) du masque métallique (55) à l'aide de la pâte à braser (17). Un substrat de relais grande capacité (21) est disposé de façon à être en contact avec les motifs correspondants de la pâte à braser (17). Un dispositif à semi-conducteur de puissance (1) est achevé par réalisation d'un traitement thermique dans des conditions de température supérieure ou égale à 200 °C.
(JA) 銅ベース板(3)に対してメタルマスク(51)が配置される。メタルマスク(51)の複数の開口部(53)に、はんだペースト(15)を充填することによって、銅ベース板(3)の銅板(5b、5c、5d)のそれぞれに、はんだペースト(15)のパターンが形成される。はんだペースト(15)のパターンに、半導体素子(9、11)および導電部品(13)が載置される。銅ベース板(3)に対してメタルマスク(55)が配置される。次に、メタルマスク(55)の複数の開口部(57)に、はんだペースト(17)を充填することによって、半導体素子(9、11)および導電部品(13)のそれぞれを覆うはんだペースト(17)のパターンが形成される。対応するはんだペースト(17)のパターンに接触するように、大容量中継基板(21)が配置される。200℃以上の温度条件のもとで熱処理を行うことによって、パワー半導体装置(1)が完成する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)