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1. (WO2018137559) POWER MODULE AND MANUFACTURING METHOD THEREFOR
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Pub. No.: WO/2018/137559 International Application No.: PCT/CN2018/073367
Publication Date: 02.08.2018 International Filing Date: 19.01.2018
IPC:
H01L 23/50 (2006.01) ,H01L 21/56 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
50
for integrated circuit devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
56
Encapsulations, e.g. encapsulating layers, coatings
Applicants:
比亚迪股份有限公司 BYD COMPANY LIMITED [CN/CN]; 中国广东省深圳市 坪山新区比亚迪路3009号 No.3009 BYD Road, Pingshan Shenzhen, Guangdong 518118, CN
Inventors:
李慧 LI, Hui; CN
杨胜松 YANG, Shengsong; CN
廖雯祺 LIAO, Wenqi; CN
杨钦耀 YANG, Qingyao; CN
李艳 LI, Yan; CN
张建利 ZHANG, Jianli; CN
曾秋莲 ZENG, Qiulian; CN
Agent:
北京集佳知识产权代理有限公司 UNITALEN ATTORNEYS AT LAW; 中国北京市 朝阳区建国门外大街22号赛特广场7层 7th Floor, Scitech Place No.22 Jian Guo Men Wai Ave. Chao Yang District Beijing 100004, CN
Priority Data:
201710063328.124.01.2017CN
Title (EN) POWER MODULE AND MANUFACTURING METHOD THEREFOR
(FR) MODULE DE PUISSANCE ET SON PROCÉDÉ DE FABRICATION
(ZH) 一种功率模块及其制造方法
Abstract:
(EN) A power module and a manufacturing method therefor, the power module comprising: an insulating dielectric substrate (10) having a first conductive layer (12) on an upper surface thereof and being provided with a heat-conduction path from a lower surface to the first conductive layer; at least one power semiconductor chip (20), wherein the chip is adhered onto the upper surface of the insulating dielectric substrate; an insulating layer (40) covering the insulating dielectric substrate and cladding the chip inside, wherein the insulating layer is provided with a through hole (42) above the chip, and the through hole is filled with a conductive substance; and a second conductive layer (50) arranged on the insulating layer, wherein the second conductive layer is electrically connected to the chip through the conductive substance. The package does not require opening a plastic packaging mould, thus saving on production costs. Additionally, a power semiconductor chip is electrically connected with an upper conductive layer by providing the through hole on the insulating layer and filling the conductive substance therein, thereby reducing the size of the module and being advantageous for miniaturizing the module.
(FR) L'invention concerne un module de puissance et son procédé de fabrication, le module de puissance comprenant : un substrat diélectrique isolant (10) ayant une première couche conductrice (12) sur une surface supérieure de celui-ci et comprenant un trajet de conduction de chaleur d'une surface inférieure à la première couche conductrice; au moins une puce semiconductrice de puissance (20), la puce étant collée sur la surface supérieure du substrat diélectrique isolant; une couche d'isolation (40) recouvrant le substrat diélectrique isolant et recouvrant la puce à l'intérieur, la couche isolante comprenant un trou traversant (42) au-dessus de la puce, et le trou traversant étant rempli d'une substance conductrice; et une seconde couche conductrice (50) disposée sur la couche d'isolation, la seconde couche conductrice étant électriquement connectée à la puce par l'intermédiaire de la substance conductrice. L'emballage ne nécessite pas l'ouverture d'un moule d'emballage en plastique, ce qui permet d'économiser en coûts de production. De plus, une puce semiconductrice de puissance est électriquement connectée à une couche conductrice supérieure par fourniture du trou traversant sur la couche d'isolation et remplissage de la substance conductrice à l'intérieur de celle-ci, réduisant ainsi la taille du module et étant avantageuse pour miniaturiser le module.
(ZH) 一种功率模块及其制造方法,功率模块包括:绝缘介质基板(10),其上表面具有第一导电层(12),且开设有从下表面到达第一导电层的导热路径;至少一个功率半导体芯片(20),芯片贴设于绝缘介质基板的上表面上;绝缘层(40),覆盖于绝缘介质基板上,将芯片包覆在内,绝缘层开设有位于芯片上方的通孔(42),且通孔内填充有导电物质;第二导电层(50),设置于绝缘层之上,第二导电层通过导电物质与芯片电气连接。封装无需开塑封模,节省了生产成本;另外,功率半导体芯片通过在绝缘层上开设通孔并填充导电物质与上层的导电层实现电气连接,减小了模块的体积,有利于模块小型化。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)