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1. (WO2018137258) LOADABLE MODULES WITH PARTIAL LINKING AND LOAD-TIME RELOCATION

Pub. No.:    WO/2018/137258    International Application No.:    PCT/CN2017/072788
Publication Date: Fri Aug 03 01:59:59 CEST 2018 International Filing Date: Tue Jan 31 00:59:59 CET 2017
IPC: G06F 12/02
Applicants: QUALCOMM INCORPORATED
CHEN, Zhi
YANG, Yusheng
Inventors: CHEN, Zhi
YANG, Yusheng
Title: LOADABLE MODULES WITH PARTIAL LINKING AND LOAD-TIME RELOCATION
Abstract:
A loadable module design that can be implemented in hardware-limited platforms. In particular, according to various aspects, literal memory space (424) may be reserved to the loadable module on a processor (610) running in an absolute addressing mode, wherein the literal space (424) may be reserved in a valid address range accessible to one or more address-restricted instructions. At build time, a partial linking combining one or more object files (320, 322, 324) associated with the loadable module with operating system exported symbols (330) may be generated. Accordingly, at load time, literal space may be allocated to the loadable module from the reserved literal memory space (424) and text and data spaces may be allocated from unused memory (440) such that addresses associated with all internal functions and variables may be relocated according to start addresses associated with the literal, text, and data spaces.