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Pub. No.: WO/2018/136802 International Application No.: PCT/US2018/014531
Publication Date: 26.07.2018 International Filing Date: 19.01.2018
IPC:
H01L 21/475 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
34
the devices having semiconductor bodies not provided for in groups H01L21/06, H01L21/16, and H01L21/18159
46
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/36-H01L21/428142
461
to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
469
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
475
using masks
Applicants: TEXAS INSTRUMENTS INCORPORATED[US/US]; P.O.BOX 655474, Mail Station 3999 Dallas, TX 75265-5474, US
TEXAS INSTRUMENTS JAPAN LIMITED[JP/JP]; 24-1, Nishi-shinjuku 6-chome Shinjuku-ku, Tokyo, 160-8366, JP (JP)
Inventors: MEIER, Sebastian; DE
RINCK, Helmut; DE
SCHACHTSCHNEIDER, Kai-alexander; DE
METZ, Fromund; DE
SCHMIDPETER, Mario; DE
MOREIRA, Javier; DE
Agent: DAVIS, Michael A. , Jr.; US
Common
Representative:
TEXAS INSTRUMENTS INCORPORATED; P.O.BOX 655474, Mail Station 3999 Dallas, TX 75265-5474, US
Priority Data:
15/658,03924.07.2017US
62/448,11019.01.2017US
Title (EN) SACRIFICIAL LAYER FOR PLATINUM PATTERNING
(FR) COUCHE SACRIFICIELLE POUR FORMATION DE MOTIFS EN PLATINE
Abstract:
(EN) At least one embodiment includes a method of patterning platinum (105B) on a substrate (101). An adhesive layer (102) is deposited over the substrate (101), a sacrificial layer (103) is deposited over the adhesive layer (102), and a patterned photoresist layer is formed over the sacrificial layer (103). Then, the sacrificial layer (103) is patterned utilizing the photoresist layer as a mask, such that at least a portion of the adhesive layer (102) is exposed. Subsequently, the top and sidewall surfaces of the patterned sacrificial layer (103) and the first portion of the adhesive layer (102) are covered by a platinum layer (105A). Finally, the sacrificial layer (103) and a portion of the platinum layer (105A) covering the top and sidewall surfaces of the sacrificial layer (103) are etched, thereby leaving a remaining portion of the platinum layer to form a patterned platinum layer (105B) on the substrate (101).
(FR) Au moins un mode de réalisation de la présente invention comprend un procédé de formation de motifs en platine (105B) sur un substrat (101). Une couche adhésive (102) est déposée sur le substrat (101), une couche sacrificielle (103) est déposée sur la couche adhésive (102), et une couche de résine photosensible à motifs est formée sur la couche sacrificielle (103). Ensuite, la couche sacrificielle (103) est modelée à l'aide de la couche de résine photosensible en tant que masque, de telle sorte qu'au moins une partie de la couche adhésive (102) est exposée. Ensuite, les surfaces supérieure et de paroi latérale de la couche sacrificielle à motifs (103) et la première partie de la couche adhésive (102) sont recouvertes d'une couche de platine (105A). Enfin, la couche sacrificielle (103) et une partie de la couche de platine (105A) recouvrant les surfaces supérieure et de paroi latérale de la couche sacrificielle (103) sont gravées, laissant ainsi une partie restante de la couche de platine pour former une couche de platine à motifs (105B) sur le substrat (101).
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)