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1. WO2018136168 - MODIFIED SELF-ALIGNED QUADRUPLE PATTERNING (SAQP) PROCESSES USING CUT PATTERN MASKS TO FABRICATE INTEGRATED CIRCUIT (IC) CELLS WITH REDUCED AREA

Publication Number WO/2018/136168
Publication Date 26.07.2018
International Application No. PCT/US2017/065569
International Filing Date 11.12.2017
IPC
H01L 27/02 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
G03F 1/70 2012.01
GPHYSICS
03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
1Originals for photomechanical production of textured or patterned surfaces, e.g. masks, photo-masks or reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
68Preparation processes not covered by groups G03F1/20-G03F1/5096
70Adapting basic layout or design of masks to lithographic process requirements, e.g. second iteration correction of mask patterns for imaging
H01L 21/033 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
027Making masks on semiconductor bodies for further photolithographic processing, not provided for in group H01L21/18 or H01L21/34165
033comprising inorganic layers
H01L 21/308 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
306Chemical or electrical treatment, e.g. electrolytic etching
308using masks
H01L 27/118 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
118Masterslice integrated circuits
CPC
G03F 7/0002
GPHYSICS
03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR;
7Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
0002Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
H01L 21/0337
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
033comprising inorganic layers
0334characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
0337characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
H01L 21/0338
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
033comprising inorganic layers
0334characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
0338Process specially adapted to improve the resolution of the mask
H01L 21/3086
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
302to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
306Chemical or electrical treatment, e.g. electrolytic etching
308using masks
3083characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
3086characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
H01L 27/0207
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
0203Particular design considerations for integrated circuits
0207Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
H01L 27/11807
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
118Masterslice integrated circuits
11803using field effect technology
11807CMOS gate arrays
Applicants
  • QUALCOMM INCORPORATED [US]/[US]
Inventors
  • SONG, Stanley, Seungchul
  • NALLAPATI, Giridhar
  • CHIDAMBARAM, Periannan
Agents
  • TERRANOVA, Steven, N.
Priority Data
15/408,79618.01.2017US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) MODIFIED SELF-ALIGNED QUADRUPLE PATTERNING (SAQP) PROCESSES USING CUT PATTERN MASKS TO FABRICATE INTEGRATED CIRCUIT (IC) CELLS WITH REDUCED AREA
(FR) PROCÉDÉS DE FORMATION DE MOTIFS QUADRUPLES AUTOALIGNÉS MODIFIÉS (SAQP) À L'AIDE DE MASQUES À MOTIFS DÉCOUPÉS POUR FABRIQUER DES CELLULES DE CIRCUIT INTÉGRÉ (CI) À SURFACE RÉDUITE
Abstract
(EN)
Aspects describing modified self-aligned quadruple patterning (SAQP) processes using cut pattern masks to fabricate integrated circuit (IC) cells with reduced area are disclosed. In one aspect, a modified SAQP process includes disposing multiple mandrels. First spacers are disposed on either side of each mandrel, and second spacers are disposed on either side of each first spacer. A cut pattern mask is disposed over the second spacers and includes openings that expose second spacers corresponding to locations in which voltage rails are to be disposed. The voltage rails are formed by removing the second spacers exposed by the openings in the cut pattern mask, and disposing the voltage rails in the corresponding locations left vacant by removing the second spacers. Routing lines are disposed over routing tracks formed between each set of the remaining second spacers to allow for interconnecting of active devices formed in the IC cell.
(FR)
L'invention concerne des aspects décrivant des procédés de formation de motifs quadruples autoalignés modifiés (SAQP) à l'aide de masques à motifs découpés pour fabriquer des cellules de circuit intégré (CI) à surface réduite. Selon un aspect, un procédé SAQP modifié consiste à disposer de multiples mandrins. Des premiers éléments d'espacement sont disposés de chaque côté de chaque mandrin, et des seconds éléments d'espacement sont disposés de chaque côté de chaque premier élément d'espacement. Un masque à motif découpé est disposé sur les seconds éléments d'espacement et comprend des ouvertures qui exposent les seconds éléments d'espacement correspondant à des emplacements dans lesquels des rails de tension doivent être disposés. Les rails de tension sont formés en retirant les seconds éléments d'espacement exposés par les ouvertures dans le masque à motif découpé, et en disposant des rails de tension dans les emplacements correspondants laissés vacants par le retrait des seconds éléments d'espacement. Des lignes de routage sont disposées sur des pistes de routage formées entre chaque ensemble des seconds éléments d'espacement restants pour permettre l'interconnexion de dispositifs actifs formés dans la cellule de CI.
Also published as
Latest bibliographic data on file with the International Bureau