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1. WO2018135088 - DATA PROCESSING DEVICE, CONVOLUTION OPERATION DEVICE, AND CONVOLUTION NEURAL NETWORK APPARATUS

Publication Number WO/2018/135088
Publication Date 26.07.2018
International Application No. PCT/JP2017/039755
International Filing Date 02.11.2017
IPC
G06F 15/80 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general; Data processing equipment in general
76Architectures of general purpose stored program computers
80comprising an array of processing units with common control, e.g. single instruction multiple data processors
G06F 9/34 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
34Addressing or accessing the instruction operand or the result
G06N 3/063 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
063using electronic means
CPC
G06F 15/80
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general
76Architectures of general purpose stored program computers
80comprising an array of processing units with common control, e.g. single instruction multiple data processors
G06F 9/345
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
34Addressing or accessing the instruction operand or the result ; ; Formation of operand address; Addressing modes
345of multiple operands or results
G06N 3/0454
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
04Architectures, e.g. interconnection topology
0454using a combination of multiple neural nets
G06N 3/063
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
063using electronic means
Applicants
  • コニカミノルタ株式会社 KONICA MINOLTA, INC. [JP]/[JP]
Inventors
  • 一倉 孝宏 ICHIKURA, Takahiro
Agents
  • 小谷 悦司 KOTANI, Etsuji
  • 小谷 昌崇 KOTANI, Masataka
  • 櫻井 智 SAKURAI, Satoshi
Priority Data
2017-00605517.01.2017JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) DATA PROCESSING DEVICE, CONVOLUTION OPERATION DEVICE, AND CONVOLUTION NEURAL NETWORK APPARATUS
(FR) DISPOSITIF DE TRAITEMENT DE DONNÉES, DISPOSITIF D'OPÉRATIONS DE CONVOLUTION, ET APPAREIL DE RÉSEAU NEURONAL À CONVOLUTION
(JA) データ処理装置、畳み込み演算装置および畳み込みニューラルネットワーク装置
Abstract
(EN)
A data processing device, a convolution operation device, and a convolution neural network apparatus according to the present invention are provided with a plurality of processor elements which are arranged in an array. Each of the processor elements is provided with a memory for storing data, and an address generator for generating a memory address for accessing the memory. The address generator sequentially generates a plurality of memory addresses, and can generate memory addresses with discontinuous changes when the memory addresses are sequentially generated.
(FR)
La présente invention concerne un dispositif de traitement de données, un dispositif d'opérations de convolution, et un appareil de réseau neuronal à convolution munis d'une pluralité d'éléments de processeur qui sont disposés en un réseau. Chacun des éléments de processeur est muni d'une mémoire servant à stocker des données, et d'un générateur d'adresses servant à générer une adresse de mémoire pour accéder à la mémoire. Le générateur d'adresses génère séquentiellement une pluralité d'adresses de mémoire, et peut générer des adresses de mémoire présentant des variations discontinues lorsque les adresses de mémoire sont générées séquentiellement.
(JA)
本発明のデータ処理装置、畳み込み演算装置および畳み込みニューラルネットワーク装置は、アレイ状に配置された複数のプロセッサエレメントを備える。前記プロセッサエレメントは、データを記憶するメモリと、前記メモリにアクセスするためのメモリアドレスを生成するアドレス生成器とを備える。前記アドレス生成器は、前記メモリアドレスを順次に複数生成し、前記メモリアドレスを順次に複数生成する際に、非連続的な変化でメモリアドレスを生成できる。
Also published as
Latest bibliographic data on file with the International Bureau