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1. WO2018134694 - COMBINING OF SEVERAL EXECUTION UNITS TO COMPUTE A SINGLE WIDE SCALAR RESULT

Publication Number WO/2018/134694
Publication Date 26.07.2018
International Application No. PCT/IB2018/050102
International Filing Date 08.01.2018
IPC
G06F 7/48 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
CPC
G06F 15/7867
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general
76Architectures of general purpose stored program computers
78comprising a single central processing unit
7867with reconfigurable architecture
G06F 15/80
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general
76Architectures of general purpose stored program computers
80comprising an array of processing units with common control, e.g. single instruction multiple data processors
G06F 7/52
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
52Multiplying; Dividing
G06F 9/3001
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
30007to perform operations on data operands
3001Arithmetic instructions
G06F 9/30014
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
30007to perform operations on data operands
3001Arithmetic instructions
30014with variable precision
G06F 9/3887
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3885using a plurality of independent parallel functional units
3887controlled by a single instruction, e.g. SIMD
Applicants
  • INTERNATIONAL BUSINESS MACHINES CORPORATION [US]/[US]
  • IBM (CHINA) INVESTMENT COMPANY LTD. [CN]/[CN] (MG)
  • IBM DEUTSCHLAND GMBH [DE]/[DE] (MG)
Inventors
  • LICHTENAU, Cedric
  • KLEIN, Michael
  • HOFMANN, Nicol
Agents
  • DOEHLER, Denis
Priority Data
15/412,42923.01.2017US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) COMBINING OF SEVERAL EXECUTION UNITS TO COMPUTE A SINGLE WIDE SCALAR RESULT
(FR) COMBINAISON DE PLUSIEURS UNITÉS D'EXÉCUTION POUR CALCULER UN SEUL RÉSULTAT SCALAIRE LARGE
Abstract
(EN)
A circuit includes reconfigurable units that are reconfigurable to compute a combined result. A first intermediate result of a first reconfigurable unit of the reconfigurable units is exchanged with a second intermediate result of the second reconfigurable unit of the reconfigurable units. The first reconfigurable unit computes a first portion of the combined result utilizing the second intermediate result. The second reconfigurable unit of the reconfigurable units computes a second portion of the combined result utilizing the first intermediate result.
(FR)
Selon l'invention, un circuit comprend des unités reconfigurables qui peuvent être reconfigurées pour calculer un résultat combiné. Un premier résultat intermédiaire d'une première unité reconfigurable des unités reconfigurables est échangé avec un second résultat intermédiaire de la seconde unité reconfigurable des unités reconfigurables. La première unité reconfigurable calcule une première partie du résultat combiné en utilisant le second résultat intermédiaire. La seconde unité reconfigurable des unités reconfigurables calcule une seconde partie du résultat combiné en utilisant le premier résultat intermédiaire.
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