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1. WO2018133057 - PACKAGING METHOD FOR WAFER-LEVEL CHIP, AND PACKAGE

Publication Number WO/2018/133057
Publication Date 26.07.2018
International Application No. PCT/CN2017/072039
International Filing Date 22.01.2017
IPC
H01L 21/56 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
56Encapsulations, e.g. encapsulating layers, coatings
H01L 23/28 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulation, e.g. encapsulating layers, coatings
H01L 23/48 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
CPC
H01L 21/563
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
H01L 21/78
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
H01L 23/28
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulations, e.g. encapsulating layers, coatings, ; e.g. for protection
H01L 23/48
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; ; Selection of materials therefor
Applicants
  • 深圳市汇顶科技股份有限公司 SHENZHEN HUIDING TECHNOLOGY CO., LTD. [CN]/[CN]
Inventors
  • 吴宝全 WU, Baoquan
  • 龙卫 LONG, Wei
  • 柳玉平 LIU, Yuping
Agents
  • 北京天奇智新知识产权代理有限公司 BEIJING TIAN QI ZHI XIN INTELLECTUAL PROPERTY AGENCY CO., LTD
Priority Data
Publication Language Chinese (ZH)
Filing Language Chinese (ZH)
Designated States
Title
(EN) PACKAGING METHOD FOR WAFER-LEVEL CHIP, AND PACKAGE
(FR) PROCÉDÉ D'EMBALLAGE POUR PUCE SUR TRANCHE, ET BOÎTIER
(ZH) 晶圆级芯片的封装方法及封装体
Abstract
(EN)
Disclosed are a packaging method for a wafer-level chip and a package relating to the technical field of semiconductors. The method comprises: attaching a wafer to a support carrier (202); reducing the thickness of the wafer; etching a scribe line (3) on the back of the wafer; adhering an insulating layer (203) to the back of the wafer and within the scribe line (2); adding a metal layer (204) to the bottom of the insulating layer (203) and of the scribe line (2); removing the metal layer (204) at the bottom of the scribe line (3); adhering a protective layer (205) to the remaining metal layer (204) and the bottom of the scribe line (3); processing the protective layer (205) to obtain adhesion holes (4), the bottom of the adhesion holes (4) being the exposed metal layer (204); and adhering solder balls (206) to the metal layer (204) at the bottom of the adhesion holes (4). A relatively thin package for the wafer-level chip can be obtained, the mechanical structure strength thereof is increased, and the requirements regarding packaging volume and packaging strength is balanced.
(FR)
L'invention concerne un procédé d'emballage pour une puce sur tranche et un boîtier se rapportant au domaine technique des semiconducteurs. Le procédé consiste à : fixer une tranche sur un dispositif de soutien (202); réduire l'épaisseur de la tranche; graver une ligne de séparation (3) sur le dos de la tranche; faire adhérer une couche isolante (203) à l'arrière de la tranche et à l'intérieur de la ligne de séparation (2); ajouter une couche métallique (204) au fond de la couche isolante (203) et de la ligne de séparation (2); retirer la couche métallique (204) au fond de la ligne de séparation (3); faire adhérer une couche protectrice (205) à la couche métallique restante (204) et au fond de la ligne de séparation (3); traiter la couche protectrice (205) pour obtenir des trous d'adhérence (4), le fond des trous d'adhérence (4) étant la couche métallique exposée (204); et faire adhérer des perles de soudure (206) à la couche métallique (204) au fond des trous d'adhérence (4). Un boîtier relativement mince pour la puce sur tranche peut être obtenu, la résistance de la structure mécanique de celui-ci est augmentée, et les exigences concernant le volume d'emballage et la force d'emballage sont équilibrées.
(ZH)
一种晶圆级芯片的封装方法及封装体,涉及半导体技术领域。所述方法包括:将晶圆片与支撑载体(202)贴合;减小所述晶圆片的厚度;在所述晶圆片的背面蚀刻划片槽(3);在所述晶圆片的背面以及所述划片槽(2)内粘附绝缘层(203);在所述绝缘层(203)以及所述划片槽(2)的底部添加金属层(204);去除所述划片槽(3)的底部的所述金属层(204);在剩余的所述金属层(204)上以及所述划片槽(3)的底部粘附保护层(205);对所述保护层(205)进行加工得到粘附孔(4),所述粘附孔(4)的底部为外露的所述金属层(204);在所述粘附孔(4)的底部的所述金属层(204)上粘附锡球(206)。能够获得相对较薄的晶圆级芯片的封装体,增加了其机械结构强度,平衡了封装体积和封装强度的要求。
Also published as
CN201780000046.5
Latest bibliographic data on file with the International Bureau