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1. WO2018132207 - INTELLIGENT REFRESH OF 3D NAND

Publication Number WO/2018/132207
Publication Date 19.07.2018
International Application No. PCT/US2017/065453
International Filing Date 08.12.2017
IPC
G11C 16/34 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
CPC
G01R 31/3171
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
317Testing of digital circuits
31708Analysis of signal quality
3171BER [Bit Error Rate] test
G06F 11/076
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
0751Error or fault detection not based on redundancy
0754by exceeding limits
076by exceeding a count or rate limit, e.g. word- or bit count limit
G06F 11/108
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
1076Parity data used in redundant arrays of independent storages, e.g. in RAID systems
108Parity data distribution in semiconductor storages, e.g. in SSD
G06F 3/0617
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from or digital output to record carriers ; , e.g. RAID, emulated record carriers, networked record carriers
0601Dedicated interfaces to storage systems
0602specifically adapted to achieve a particular effect
0614Improving the reliability of storage systems
0617in relation to availability
G06F 3/0659
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from or digital output to record carriers ; , e.g. RAID, emulated record carriers, networked record carriers
0601Dedicated interfaces to storage systems
0628making use of a particular technique
0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
0659Command handling arrangements, e.g. command buffers, queues, command scheduling
G06F 3/0688
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from or digital output to record carriers ; , e.g. RAID, emulated record carriers, networked record carriers
0601Dedicated interfaces to storage systems
0668adopting a particular infrastructure
0671In-line storage system
0683Plurality of storage devices
0688Non-volatile semiconductor memory arrays
Applicants
  • PURE STORAGE, INC. [US]/[US]
Inventors
  • KANNAN, Hari
  • LEE, Robert
  • MAO, Yuhong
Agents
  • GENCARELLA, Michael L.
  • OVANEZIAN, Daniel E.
  • CHEN, Tony T.
  • KOKOSKA, Christopher
  • JACOBS, JR., William D.
Priority Data
15/406,48413.01.2017US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) INTELLIGENT REFRESH OF 3D NAND
(FR) RAFRAÎCHISSEMENT INTELLIGENT DE NON-ET 3D
Abstract
(EN)
A method for processing blocks of flash memory to decrease raw bit errors from the flash memory is provided. The method includes identifying one or more blocks of the flash memory for a refresh operation and writing information regarding the identified blocks, to a data structure. The method includes issuing background reads to the identified blocks, according to the data structure, as the refresh operation. The method may be embodied on a computer readable medium. In some embodiments the background reads may be based on a time based refresh responsive to an increase in raw bit error count in the flash memory over time.
(FR)
L'invention concerne également un procédé de traitement de blocs de mémoire flash afin de diminuer les erreurs de bits brutes à partir de la mémoire flash. Le procédé consiste à identifier un ou plusieurs blocs de la mémoire flash pour une opération de rafraîchissement et à écrire des informations concernant les blocs identifiés, à une structure de données. Le procédé consiste à émettre des lectures d'arrière-plan aux blocs identifiés, en fonction de la structure de données, en tant qu'opération de rafraîchissement. Le procédé peut être incorporé sur un support lisible par ordinateur. Selon certains modes de réalisation, les lectures d'arrière-plan peuvent être basées sur un rafraîchissement basé sur le temps en réponse à une augmentation du nombre d'erreurs de bits brutes dans la mémoire flash au fil du temps.
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