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1. (WO2018128857) METHODS OF FORMING AN ARRAY OF CAPACITORS, METHODS OF FORMING AN ARRAY OF MEMORY CELLS INDIVIDUALLY COMPRISING A CAPACITOR AND A TRANSISTOR, ARRAYS OF CAPACITORS, AND ARRAYS OF MEMORY CELLS INDIVIDUALLY COMPRISING A CAPACITOR AND A TRANSISTOR
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Pub. No.: WO/2018/128857 International Application No.: PCT/US2017/068197
Publication Date: 12.07.2018 International Filing Date: 22.12.2017
IPC:
H01L 27/108 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
108
Dynamic random access memory structures
Applicants:
MICRON TECHNOLOGY, INC. [US/US]; (a Corporation of the State of Delaware) 8000 South Federal Way Boise, ID 83716, US
Inventors:
RAMASWAMY, Durai Vishak, Nirmal; US
Agent:
MATKIN, Mark, S.; US
GRZELAK, Keith, D.; US
SHAURETTE, James, D.; US
HENDRICKSEN, Mark, W.; US
LATWESEN, David, G.; US
Priority Data:
15/401,37209.01.2017US
Title (EN) METHODS OF FORMING AN ARRAY OF CAPACITORS, METHODS OF FORMING AN ARRAY OF MEMORY CELLS INDIVIDUALLY COMPRISING A CAPACITOR AND A TRANSISTOR, ARRAYS OF CAPACITORS, AND ARRAYS OF MEMORY CELLS INDIVIDUALLY COMPRISING A CAPACITOR AND A TRANSISTOR
(FR) PROCÉDÉS DE FORMATION D'UN RÉSEAU DE CONDENSATEURS, PROCÉDÉS DE FORMATION D'UN RÉSEAU DE CELLULES DE MÉMOIRE COMPRENANT INDIVIDUELLEMENT UN CONDENSATEUR ET UN TRANSISTOR, RÉSEAUX DE CONDENSATEURS, ET RÉSEAUX DE CELLULES DE MÉMOIRE COMPRENANT INDIVIDUELLEMENT UN CONDENSATEUR ET UN TRANSISTOR
Abstract:
(EN) A method of forming an array of capacitors comprises forming elevationally-extending and longitudinally-elongated capacitor electrode lines over a substrate. Individual of the capacitor electrode lines are common to and a shared one of two capacitor electrodes of individual capacitors longitudinally along a line of capacitors being formed. A capacitor insulator is formed over a pair of laterally-opposing sides of and longitudinally along individual of the capacitor electrode lines. An elevationally-extending conductive line is formed over the capacitor insulator longitudinally along one of the laterally-opposing sides of the individual capacitor electrode lines. The conductive line is cut laterally through to form spaced individual other of the two capacitor electrodes of the individual capacitors. Other methods are disclosed, including structures independent of method of manufacture.
(FR) Un procédé de formation d'un réseau de condensateurs comprend la formation de lignes d'électrodes de condensateur s'étendant en hauteur et allongées longitudinalement sur un substrat. Des lignes d’électrode de condensateur individuelles des lignes d'électrodes de condensateur sont communes et sont partagées avec deux électrodes de condensateur de condensateurs individuels longitudinalement le long de condensateurs étant formés. Un isolateur de condensateur est formé sur une paire de côtés latéralement opposés et longitudinalement le long de lignes d'électrode de condensateur individuelles. Une ligne conductrice s'étendant en hauteur est formée sur l'isolant de condensateur longitudinalement le long d'un des côtés latéralement opposés des lignes d'électrodes de condensateur individuelles. La ligne conductrice est découpée latéralement pour former d'autres électrodes individuelles espacées des deux électrodes de condensateur des condensateurs individuels. L'invention concerne également d'autres procédés, comprenant des structures indépendantes du procédé de fabrication.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)