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1. (WO2018127726) DELAY ELEMENT CIRCUIT FOR RING OSCILLATOR AND STALL DETECTION IN SELF-CLOCKED SAR ADC
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Pub. No.: WO/2018/127726 International Application No.: PCT/IB2017/000342
Publication Date: 12.07.2018 International Filing Date: 16.03.2017
IPC:
H03M 1/00 (2006.01) ,H03K 3/03 (2006.01) ,H03M 1/12 (2006.01) ,H03M 1/46 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
M
CODING, DECODING OR CODE CONVERSION, IN GENERAL
1
Analogue/digital conversion; Digital/analogue conversion
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
3
Circuits for generating electric pulses; Monostable, bistable or multistable circuits
02
Generators characterised by the type of circuit or by the means used for producing pulses
027
by the use of logic circuits, with internal or external positive feedback
03
Astable circuits
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
M
CODING, DECODING OR CODE CONVERSION, IN GENERAL
1
Analogue/digital conversion; Digital/analogue conversion
12
Analogue/digital converters
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
M
CODING, DECODING OR CODE CONVERSION, IN GENERAL
1
Analogue/digital conversion; Digital/analogue conversion
12
Analogue/digital converters
34
Analogue value compared with reference values
38
sequentially only, e.g. successive approximation type
46
with digital/analogue converter for supplying reference values to converter
Applicants:
DISRUPTIVE TECHNOLOGIES RESEARCH AS [NO/NO]; Laguneveien 7 5239 Radal, NO
MOLDSVOR, Oystein [NO/NO]; NO
Inventors:
HERNES, Bjornar; NO
Priority Data:
15/400,53406.01.2017US
Title (EN) DELAY ELEMENT CIRCUIT FOR RING OSCILLATOR AND STALL DETECTION IN SELF-CLOCKED SAR ADC
(FR) CIRCUIT À ÉLÉMENT À RETARD DESTINÉ À UN OSCILLATEUR EN ANNEAU ET À LA DÉTECTION DE DÉCROCHAGE DANS UN CAN À SAR AUTO-CADENCÉ
Abstract:
(EN) A self-clocked SAR ADC sensor circuit includes an ADC having a capacitor array with a plurality of capacitors connected through a respective plurality of switches, a comparator, an SAR module, and a delay element circuit for ring oscillator and stall detection. The delay element circuit includes a delay block with a NAND gate followed by a plurality of inverters.
(FR) La présente invention concerne un circuit de capteur CAN à SAR auto-cadencé, comprenant un CAN doté d'un réseau de condensateurs présentant une pluralité de condensateurs connectés au moyen d'une pluralité respective de commutateurs, un comparateur, un module SAR, et un circuit à élément à retard destiné à un oscillateur en anneau et à la détection de décrochage. Le circuit à élément à retard comprend un bloc de retard présentant une porte NON-ET suivi d'une pluralité d'onduleurs.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)