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1. (WO2018126703) DUAL-GATE THIN-FILM TRANSISTOR AND PREPARATION METHOD THEREFOR, ARRAY SUBSTRATE AND DISPLAY APPARATUS

Pub. No.:    WO/2018/126703    International Application No.:    PCT/CN2017/098307
Publication Date: Fri Jul 13 01:59:59 CEST 2018 International Filing Date: Tue Aug 22 01:59:59 CEST 2017
IPC: H01L 29/786
H01L 21/336
H01L 21/34
Applicants: BOE TECHNOLOGY GROUP CO., LTD.
京东方科技集团股份有限公司
BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
北京京东方显示技术有限公司
Inventors: QU, Lianjie
曲连杰
BAI, Jinchao
白金超
Title: DUAL-GATE THIN-FILM TRANSISTOR AND PREPARATION METHOD THEREFOR, ARRAY SUBSTRATE AND DISPLAY APPARATUS
Abstract:
A dual-gate thin-film transistor and a preparation method therefor, an array substrate and a display apparatus. The dual-gate thin-film transistor comprises: a base substrate (10), and a first gate electrode (130), a first gate insulation layer (120), an active layer (15), a second gate insulation layer (121, 122, 123), a first electrode (160, 162, 164), a second electrode (161, 163, 165), a second gate electrode (131) and a connection electrode (18, 180), which are arranged on the base substrate (10). The second gate electrode (131), the first electrode (160, 162, 164) and the second electrode (161, 163, 165) are formed on the same layer. The first gate insulation layer (120) comprises a first via hole (20) exposing a part of the first gate electrode (130), and the connection electrode (18, 180) is electrically connected to the second gate electrode (131) and is electrically connected to the first gate electrode (130) through the first via hole (20). In the dual-gate thin-film transistor, the first electrode (160, 162, 164), the second electrode (161, 163, 165) and the second gate electrode (131) are formed at the same time by means of one photolithography process. The connection electrode (18, 180) is electrically connected to the first gate electrode (130) and the second gate electrode (131) so as to realize a dual-gate structure, thereby reducing the number of film layers and masks, and production costs, improving the stability of the thin-film transistor and optimizing the response speed of the thin-film transistor.