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1. WO2018126542 - POP (PACKAGE ON PACKAGE) STRUCTURE AND TERMINAL

Publication Number WO/2018/126542
Publication Date 12.07.2018
International Application No. PCT/CN2017/078636
International Filing Date 29.03.2017
IPC
H01L 25/00 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 23/13 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
12Mountings, e.g. non-detachable insulating substrates
13characterised by the shape
H01L 23/31 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulation, e.g. encapsulating layers, coatings
31characterised by the arrangement
CPC
H01L 2224/16145
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
161Disposition
16135the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
16145the bodies being stacked
H01L 2224/16225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
161Disposition
16151the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
16221the body and the item being stacked
16225the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L 2224/32145
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32135the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
32145the bodies being stacked
H01L 23/13
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
12Mountings, e.g. non-detachable insulating substrates
13characterised by the shape
H01L 23/31
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulations, e.g. encapsulating layers, coatings, ; e.g. for protection
31characterised by the arrangement ; or shape
H01L 25/00
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; ; Multistep manufacturing processes thereof
Applicants
  • 华为技术有限公司 HUAWEI TECHNOLOGIES CO., LTD. [CN]/[CN]
Inventors
  • 史洪宾 SHI, Hongbin
  • 叶润清 YE, Runqing
  • 龙浩晖 LONG, Haohui
Agents
  • 北京同达信恒知识产权代理有限公司 TDIP & PARTNERS
Priority Data
201710005412.804.01.2017CN
Publication Language Chinese (ZH)
Filing Language Chinese (ZH)
Designated States
Title
(EN) POP (PACKAGE ON PACKAGE) STRUCTURE AND TERMINAL
(FR) STRUCTURE POP ( BOÎTIER SUR BOÎTIER) ET BORNE
(ZH) 一种堆叠封装结构及终端
Abstract
(EN)
Disclosed are a PoP (package on package) structure and a terminal. The PoP structure comprises: a main board (10) and at least two package layers arranged in a stacked manner along the direction away from the main board, wherein the package layer, closest to one side of the main board, in the at least two package layers is in welded connection with the main board; the package layer, close to one side of the main board, in any two adjacent package layers is a lower package layer (20), and the package layer away from one side of the main board is an upper package layer (30); the lower package layer is in welded connection with the upper package layer; a first adhesive pouring layer (40) is also arranged between the lower package layer and the upper package layer; a first adhesive pouring area (21) corresponding to the first adhesive pouring layer is arranged in the lower package layer; and the first adhesive pouring area does not overlap with the upper package layer. During dispensing, a dispensing material is dripped in the first adhesive pouring area of the lower package layer, after the dispensing material fully fills the first adhesive pouring area, dispensing is stopped, and the first adhesive pouring layer is formed after the dispensing material is cured, thus solving the problem in the prior art that a space between the lower package layer and the upper package layer is difficult to fill completely or is easily filled partially.
(FR)
L'invention concerne une structure PoP (boîtier sur boîtier) et une borne. La structure PoP comprend : une carte principale (10) et au moins deux couches d'emballage agencées de manière empilée le long de la direction à l'opposé de la carte principale, la couche d'emballage, la plus proche d'un côté de la carte principale, dans lesdites au moins deux couches d'emballage étant en liaison soudée avec la carte principale; la couche d'emballage, proche d'un côté de la carte principale, dans toutes les deux couches d'emballage adjacentes est une couche d'emballage inférieure (20), et la couche d'emballage à l'opposé d'un côté de la carte principale est une couche d'emballage supérieure (30); la couche d'emballage inférieure est en liaison soudée avec la couche d'emballage supérieure; une première couche de versage adhésive (40) est également disposée entre la couche d'emballage inférieure et la couche d'emballage supérieure; une première zone de versage adhesive (21) correspondant à la première couche de versage adhésive est disposée dans la couche d'emballage inférieure; et la première zone de versage adhésive ne chevauche pas la couche d'emballage supérieure. Pendant la distribution, un matériau de distribution est égoutté dans la première zone de versage adhésive de la couche d'emballage inférieure, après que le matériau de distribution remplit complètement la première zone de versage adhésive, la distribution est arrêtée, et la première couche de versage adhésive est formée après que le matériau de distribution a été durci, ce qui permet de résoudre le problème dans l'état de la technique selon lequel un espace entre la couche d'emballage inférieure et la couche d'emballage supérieure est difficile à remplir complètement ou est facilement rempli partiellement.
(ZH)
一种堆叠封装结构及终端,该堆叠封装结构包括:主板(10)以及沿远离主板的方向层叠设置的至少两个封装层,其中,至少两个封装层中最靠近主板一侧的封装层与主板焊接连接;任意相邻的两个封装层中靠近主板一侧的封装层为下封装层(20),远离主板一侧的封装层为上封装层(30),下封装层与上封装层焊接连接;下封装层与上封装层之间还设有第一灌胶层(40),下封装层中设有与第一灌胶层相对应的第一灌胶区(21),且第一灌胶区与上封装层不重叠。在进行点胶时,将点胶材料滴落在下封装层的第一灌胶区,待点胶材料充分填充后停止点胶,点胶材料固化后形成第一灌胶层,解决现有技术中下封装层与上封装层之间完全填充难或容易部分填充的问题。
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