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1. (WO2018126508) METHOD FOR MANUFACTURING TFT SUBSTRATE
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Pub. No.: WO/2018/126508 International Application No.: PCT/CN2017/073330
Publication Date: 12.07.2018 International Filing Date: 13.02.2017
IPC:
H01L 21/77 (2017.01) ,H01L 27/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
Applicants:
深圳市华星光电技术有限公司 SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. [CN/CN]; 中国广东省深圳市 光明新区塘明大道9-2号谭玉 TAN Yu NO.9-2 Tangming Rd, Guangming New District Shenzhen, Guangdong 518132, CN
Inventors:
卢马才 LU, Macai; CN
姚江波 YAO, Jiangbo; CN
覃事建 QIN, Shijian; CN
Agent:
深圳翼盛智成知识产权事务所(普通合伙) ESSEN PATENT & TRADEMARK AGENCY; 中国广东省深圳市 福田区深南大道6021号喜年中心A座1709-1711 Hailrun Complex Block A Room 1709-1711 No.6021 Shennan Blvd, Futian District ShenZhen, Guangdong 518040, CN
Priority Data:
201710002056.403.01.2017CN
Title (EN) METHOD FOR MANUFACTURING TFT SUBSTRATE
(FR) PROCÉDÉ DE FABRICATION DE SUBSTRAT DE TRANSISTOR À COUCHES MINCES
(ZH) TFT基板的制作方法
Abstract:
(EN) A method for manufacturing a TFT substrate, comprising: forming a TFT gate electrode (101) on a substrate (1000); then, successively forming a first insulation layer (20), an active layer (30), a source electrode (401) and a drain electrode (402); then, forming a second insulation layer (50) and coating a photoresist (60); defining a pixel electrode pattern; forming a drain through hole (B) on the second insulation layer (50); depositing a pixel electrode layer (70) after photoresist texturing; and a peeling liquid permeating same from a textured surface to remove the photoresist (60) and the pixel electrode layer (70) on the photoresist (60), so as to form a pixel electrode (70), such that the pixel electrode (70) is connected to the drain electrode (402) via the drain through hole (B).
(FR) L'invention concerne un procédé de fabrication d'un substrat de transistor à couches minces, consistant à : former une électrode de grille de transistor à couches minces (101) sur un substrat (1000) ; puis former successivement une première couche d'isolation (20), une couche active (30), une électrode de source (401) et une électrode de drain (402) ; puis former une seconde couche d'isolation (50) et revêtir une résine photosensible (60) ; définir un motif d'électrode de pixel ; former un trou traversant de drain (B) sur la seconde couche d'isolation (50) ; déposer une couche d'électrode de pixel (70) après la texturation de résine photosensible ; et un liquide de pelage pénétrant dans celle-ci à partir d'une surface texturée pour retirer la résine photosensible (60) et la couche d'électrode de pixel (70) sur la résine photosensible (60), de manière à former une électrode de pixel (70), de telle sorte que l'électrode de pixel (70) est connectée à l'électrode de drain (402) par l'intermédiaire du trou traversant de drain (B).
(ZH) 一种TFT基板的制作方法,包括:在基板(1000)上形成TFT栅极(101),再依次形成第一绝缘层(20)、有源层(30)、源极(401)和漏极(402),再形成第二绝缘层(50)并涂布光阻(60),定义像素电极图案,在第二绝缘层(50)上形成漏极通孔(B),光阻制绒后沉积像素电极层(70),从绒面渗入剥离液去除光阻(60)及光阻(60)上的像素电极层(70),形成像素电极(70),使像素电极(70)通过漏极通孔(B)与漏极(402)相连。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)