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1. (WO2018125679) SUBSTRATE WITH GRADIATED DIELECTRIC FOR REDUCING IMPEDANCE MISMATCH

Pub. No.:    WO/2018/125679    International Application No.:    PCT/US2017/067366
Publication Date: Fri Jul 06 01:59:59 CEST 2018 International Filing Date: Wed Dec 20 00:59:59 CET 2017
IPC: H05K 1/02
H05K 1/11
Applicants: INTEL CORPORATION
Inventors: KONG, Jackson Chung Peng
CHEAH, Bok Eng
OOI, Ping Ping
OOI, Kooi Chi
Title: SUBSTRATE WITH GRADIATED DIELECTRIC FOR REDUCING IMPEDANCE MISMATCH
Abstract:
An electronic circuit including a substrate having a first dielectric characteristic. The substrate can include a first side and a second side. An intermediary material can be disposed within the substrate. For instance, the intermediary material can be located between the first side and the second side. The intermediary material can include a second dielectric characteristic, where the second dielectric characteristic is different than the first dielectric characteristic. A first conductive layer can be disposed on the first side, and a second conductive layer can be disposed on the second side. A conductive path can be electrically coupled between the first conductive layer and the second conductive layer. The conductive path can be in contact with at least a portion of the intermediary material.