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1. (WO2018125623) NEURAL NETWORK PROCESSOR
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CLAIMS

1. An integrated circuit, comprising:

an N-way single-instruction multiple data (SIMD) array of processors where each processor of the array includes a multiply-accumulate unit having a respective accumulator;

a crossbar to provide a respective selected neural network input value to each of the N processors, the N number of selected neural network input values selected from M number of input values.

2. The integrated circuit of claim 1, wherein M>N.

3. The integrated circuit of claim 1, further comprising:

an instruction memory to provide a first index to address a first memory, the

respective input value provided to each of the N processors being based on the output of the first memory.

4. The integrated circuit of claim 3, wherein the instruction memory to also provide a second index to address a second memory, a respective coefficient value to be provided to each of the N processors being based on the output of the second memory.

5. The integrated circuit of claim 1, wherein the N-way SIMD array of processors can be configured to operate using X number of processors, where N>X.

6. A method of computing, in parallel, a plurality of neuron outputs of a neural network, comprising:

receiving a plurality of neural network input values;

providing, from a first memory and based on a first index, a first plurality of neural network weights to a corresponding plurality of multiply-accumulate units; receiving, from a second memory and based on a second index, a plurality of

crossbar control values that associate each of the plurality of neural network input values to the respective ones of the plurality of multiply- accumulate units;

based on the plurality of crossbar control values, providing the plurality of neural network input values to the to the respective ones of the plurality of multiply-accumulate units;

performing, in parallel and by the plurality of multiply-accumulate units,

respective multiply-accumulate operations using the respective first plurality of neural network weights and the respective plurality of neural network input values.

7. The method of claim 6, further comprising:

receiving, from an instruction memory, the first index.

8. The method of claim 6, further comprising:

receiving, from an instruction memory, the second index.

9. The method of claim 6, wherein the first index and the second index are associated with an instruction by an instruction memory.

10. An integrated circuit, comprising:

a plurality of multiply-accumulate units to receive respective first operands and respective second operands;

a first memory to provide, based on a first index, a corresponding plurality of respective second operands to the plurality of multiply-accumulate units; a crossbar to provide a corresponding plurality of respective first operands to the plurality of multiply-accumulate units;

a second memory to control, based on a second index, the crossbar to provide, from a plurality of sources, the corresponding plurality of respective first operands to the plurality of multiply-accumulate units.

11. The integrated circuit of claim 10, further comprising:

a third memory to provide a plurality of first indexes to the first memory.

12. The integrated circuit of claim 10, further comprising:

a third memory to provide a plurality of second indexes to the second memory.

13. The integrated circuit of claim 10, further comprising:

a third memory to provide a plurality of first indexes to the first memory and a plurality of second indexes to the second memory.

14. The integrated circuit of claim 13, wherein the third memory also determines whether the plurality of multiply-accumulate units perform multiply-accumulate operations.

15. The integrated circuit of claim 13, wherein the third memory also determines a number of the plurality of multiply-accumulate units that are to perform multiply-accumulate operations.