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1. (WO2018125546) MULTIPLE VIA STRUCTURE FOR HIGH PERFORMANCE STANDARD CELLS

Pub. No.:    WO/2018/125546    International Application No.:    PCT/US2017/065429
Publication Date: Fri Jul 06 01:59:59 CEST 2018 International Filing Date: Sat Dec 09 00:59:59 CET 2017
IPC: H01L 27/02
H01L 23/528
H01L 27/118
Applicants: QUALCOMM INCORPORATED
Inventors: SAHU, Satyanarayana
CHEN, Xiangdong
BOYNAPALLI, Venugopal
LIM, Hyeokjin
MALABRY, Mickael
GUPTA, Mukul
Title: MULTIPLE VIA STRUCTURE FOR HIGH PERFORMANCE STANDARD CELLS
Abstract:
A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.