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1. (WO2018125487) SEMICONDUCTOR CHIP PACKAGE WITH CAVITY

Pub. No.:    WO/2018/125487    International Application No.:    PCT/US2017/063671
Publication Date: Fri Jul 06 01:59:59 CEST 2018 International Filing Date: Thu Nov 30 00:59:59 CET 2017
IPC: H01L 23/04
H01L 25/16
H01L 25/07
H01L 23/12
H01L 23/485
H01L 23/00
Applicants: INTEL CORPORATION
Inventors: GOGINENI, Sireesha
DOMINGUEZ, Juan Eduardo
Title: SEMICONDUCTOR CHIP PACKAGE WITH CAVITY
Abstract:
Various embodiments disclosed relate to a semiconductor package. The semiconductor package includes a substrate having first and second opposed major surfaces. The substrate further includes a cavity having a first end defined by a portion of the first major surface and a second end defined by a portion of the second major surface. The semiconductor package further includes a first electronic component attached to the first major surface. The first electronic component substantially covers the first end of the cavity. A second electronic component is at least partially disposed within the cavity.