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1. (WO2018125449) POST-GRIND DIE BACKSIDE POWER DELIVERY
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Pub. No.: WO/2018/125449 International Application No.: PCT/US2017/063284
Publication Date: 05.07.2018 International Filing Date: 27.11.2017
IPC:
H01L 25/065 (2006.01) ,H01L 23/485 (2006.01) ,H01L 23/48 (2006.01) ,H01L 23/538 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
482
consisting of lead-in layers inseparably applied to the semiconductor body
485
consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
538
the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
LAI, Min-Tih Ted; US
LEUTEN, Tyler; US
PON, Florence R,; US
Agent:
PERDOK, Monique M.; US
SCHEER, Bradley W., Reg. No. 47,059; US
WOO, Justin, N., Reg. No. 62,686; US
MCCRACKIN, Ann M., Reg. No. 42,858; US
GOULD, James R., Reg. No. 72,086; US
BLACK, David W., Reg. No. 42,331; US
BIANCHI, Timothy E., Reg. No. 39,610; US
BEEKMAN, Marvin L., Reg. No. 38,377; US
ARORA, Suneel, Reg. No. 42,267; US
Priority Data:
15/391,58727.12.2016US
Title (EN) POST-GRIND DIE BACKSIDE POWER DELIVERY
(FR) DISTRIBUTION D'ÉNERGIE SUR LE CÔTÉ ARRIÈRE D'UNE PUCE APRÈS MEULAGE
Abstract:
(EN) Disclosed is a die. The die may include a material layer, a plurality of vias, and a plurality of metal channels. The material layer may have a top side and a backside. The top side may include a plurality of pad connections. The plurality of vias may extend through the material layer from the top side to the backside. The plurality of metal channels may be in contact with the backside. Each of the plurality of metal channels may be in electrical communication with at least one of the plurality of pad connections and at least one of the plurality of vias.
(FR) Cette invention concerne une puce. La puce peut comprendre une couche de matériau, une pluralité de trous d'interconnexion, et une pluralité de canaux métalliques. La couche de matériau peut avoir un côté supérieur et un côté arrière. Le côté supérieur peut comprendre une pluralité de plots de connexion. La pluralité de trous d'interconnexion peut s'étendre à travers la couche de matériau, du côté supérieur au côté arrière. La pluralité de canaux métalliques peut être en contact avec le côté arrière. Chaque canal de la pluralité de canaux métalliques peut être en communication électrique avec au moins l'un de la pluralité de plots de connexion et au moins l'un de la pluralité de trous d'interconnexion.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)