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1. (WO2018125411) METHODS OF FORMING PACKAGE STRUCTURES FOR ENHANCED MEMORY CAPACITY AND STRUCTURES FORMED THEREBY

Pub. No.:    WO/2018/125411    International Application No.:    PCT/US2017/061733
Publication Date: Fri Jul 06 01:59:59 CEST 2018 International Filing Date: Thu Nov 16 00:59:59 CET 2017
IPC: H01L 25/065
H01L 23/498
H01L 23/538
Applicants: INTEL CORPORATION
Inventors: SINGH, Navneet K.
THOMAS, Shanto A.
BALAKRISHNAN, Ranjul
Title: METHODS OF FORMING PACKAGE STRUCTURES FOR ENHANCED MEMORY CAPACITY AND STRUCTURES FORMED THEREBY
Abstract:
Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a die on a board, attaching a substrate on the die, wherein the substrate comprises a first region and a peripheral region, attaching a first memory device on the central region of the substrate, and attaching at least one additional memory device on the peripheral region of the substrate, wherein the at least one additional memory device is not disposed over the die.