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1. (WO2018125401) MULTI LEVEL SYSTEM MEMORY HAVING DIFFERENT CACHING STRUCTURES AND MEMORY CONTROLLER THAT SUPPORTS CONCURRENT LOOK-UP INTO THE DIFFERENT CACHING STRUCTURES

Pub. No.:    WO/2018/125401    International Application No.:    PCT/US2017/061385
Publication Date: Fri Jul 06 01:59:59 CEST 2018 International Filing Date: Tue Nov 14 00:59:59 CET 2017
IPC: G06F 12/0802
Applicants: INTEL CORPORATION
Inventors: DIAMAND, Israel
GREENFIELD, Zvika
MANDELBLAT, Julius Yuli
RUBINSTEIN, Asaf
Title: MULTI LEVEL SYSTEM MEMORY HAVING DIFFERENT CACHING STRUCTURES AND MEMORY CONTROLLER THAT SUPPORTS CONCURRENT LOOK-UP INTO THE DIFFERENT CACHING STRUCTURES
Abstract:
An apparatus is described. The apparatus includes a memory controller to interface to a multi- level system memory having first and second different cache structures. The memory controller has circuitry to service a read request by concurrently performing a look-up into the first and second different cache structures for a cache line that is targeted by the read request.