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1. (WO2018125206) AMBIPOLAR LAYER BASED ACCESS TRANSISTORS FOR MEMORY APPLICATIONS AND METHODS OF FABRICATION
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Pub. No.: WO/2018/125206 International Application No.: PCT/US2016/069477
Publication Date: 05.07.2018 International Filing Date: 30.12.2016
IPC:
H01L 29/73 (2006.01) ,H01L 29/66 (2006.01) ,H01L 29/78 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
70
Bipolar devices
72
Transistor-type devices, i.e. able to continuously respond to applied control signals
73
Bipolar junction transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
PILLARISETTY, Ravi; US
MAJHI, Prashant; US
KARPOV, Elijah V.; US
MUKHERJEE, Niloy; US
Agent:
BRASK, Justin, K.; US
Priority Data:
Title (EN) AMBIPOLAR LAYER BASED ACCESS TRANSISTORS FOR MEMORY APPLICATIONS AND METHODS OF FABRICATION
(FR) TRANSISTORS D'ACCÈS À BASE DE COUCHE AMBIPOLAIRE POUR DES APPLICATIONS DE MÉMOIRE ET PROCÉDÉS DE FABRICATION
Abstract:
(EN) A 1T-1R memory cell includes a transistor structure where an ambipolar layer is disposed on an insulator layer formed on a substrate. The transistor further includes a gate dielectric layer that is disposed on the ambipolar layer and a gate electrode disposed on the gate dielectric layer. A source region and a drain region are disposed on the ambipolar layer. The source region is separated from the drain region by the gate electrode. A source contact is disposed on the source region and a drain contact disposed on the drain region. The 1T-1R cell further includes a memory device that is disposed above the drain contact of the transistor. The memory device belongs to a class of memory devices that is based on resistive switching.
(FR) Selon la présente invention, une cellule de mémoire 1T-1R comprend une structure de transistor dans laquelle une couche ambipolaire est disposée sur une couche isolante formée sur un substrat. Le transistor comprend en outre une couche diélectrique de grille qui est disposée sur la couche ambipolaire et une électrode de grille disposée sur la couche diélectrique de grille. Une région de source et une région de drain sont disposées sur la couche ambipolaire. La région de source est séparée de la région de drain par l'électrode de grille. Un contact de source est disposé sur la région de source et un contact de drain est disposé sur la région de drain. La cellule 1T-1R comprend en outre un dispositif de mémoire qui est disposé au-dessus du contact de drain du transistor. Le dispositif de mémoire appartient à une classe de dispositifs de mémoire qui est basée sur une commutation résistive.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)