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1. (WO2018125170) SEMICONDUCTOR PACKAGE HAVING WAFER-LEVEL ACTIVE DIE AND EXTERNAL DIE MOUNT
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Pub. No.: WO/2018/125170 International Application No.: PCT/US2016/069344
Publication Date: 05.07.2018 International Filing Date: 29.12.2016
IPC:
H01L 23/31 (2006.01) ,H01L 23/00 (2006.01) ,H01L 23/525 (2006.01) ,H01L 23/48 (2006.01) ,H01L 21/768 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
28
Encapsulation, e.g. encapsulating layers, coatings
31
characterised by the arrangement
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
525
with adaptable interconnections
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
MEHTA, Vipul Vijay; US
LI, Eric Jin; US
GANESAN, Sanka; US
MALLIK, Debendra; US
SANKMAN, Robert Leon; US
Agent:
BRASK, Justin, K.; US
Priority Data:
Title (EN) SEMICONDUCTOR PACKAGE HAVING WAFER-LEVEL ACTIVE DIE AND EXTERNAL DIE MOUNT
(FR) BOÎTIER DE SEMI-CONDUCTEUR AYANT UNE PUCE ACTIVE AU NIVEAU D'UNE TRANCHE ET SUPPORT DE PUCE EXTERNE
Abstract:
(EN) Semiconductor packages and package assemblies having active dies and external die mounts on a silicon wafer, and methods of fabricating such semiconductor packages and package assemblies, are described. In an example, a semiconductor package assembly includes a semiconductor package having an active die attached to a silicon wafer by a first solder bump. A second solder bump is on the silicon wafer laterally outward from the active die to provide a mount for an external die. An epoxy layer may surround the active die and cover the silicon wafer. A hole may extend through the epoxy layer above the second solder bump to expose the second solder bump through the hole. Accordingly, an external memory die can be connected directly to the second solder bump on the silicon wafer through the hole.
(FR) La présente invention concerne des boîtiers de semi-conducteur et des ensembles boîtiers ayant des puces actives et des supports de puce externes sur une tranche de silicium, et leurs procédés de fabrication. Dans un exemple, un ensemble boîtier de semi-conducteur comprend un boîtier de semi-conducteur ayant une puce active fixée à une tranche de silicium par une première perle de soudure. Une seconde perle de soudure se trouve sur la tranche de silicium latéralement vers l'extérieur à partir de la puce active pour fournir un support pour une puce externe. Une couche époxy peut entourer la puce active et recouvrir la tranche de silicium. Un trou peut s'étendre à travers la couche époxy au-dessus de la seconde perle de soudure pour exposer la seconde perle de soudure à travers le trou. Par conséquent, une puce de mémoire externe peut être connectée directement à la seconde perle de soudure sur la tranche de silicium à travers le trou.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)