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1. WO2018125142 - PROTECTION LAYERS FOR MAGNETIC TUNNEL JUNCTIONS

Publication Number WO/2018/125142
Publication Date 05.07.2018
International Application No. PCT/US2016/069222
International Filing Date 29.12.2016
IPC
H01L 43/02 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
43Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
02Details
H01L 43/08 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
43Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
08Magnetic-field-controlled resistors
H01L 43/10 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
43Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
10Selection of materials
H01L 43/12 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
43Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
12Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
CPC
H01L 43/02
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
43Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
02Details
H01L 43/08
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
43Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
08Magnetic-field-controlled resistors
H01L 43/10
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
43Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
10Selection of materials
H01L 43/12
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
43Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
12Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
Applicants
  • INTEL CORPORATION [US]/[US]
Inventors
  • O'BRIEN, Kevin P.
  • CLENDENNING, Scott B.
  • OGUZ, Kaan
  • DOCZY, Mark L.
  • DOYLE, Brian S.
  • RAHMAN, Tofizur
  • WIEGAND, Christopher J.
  • GOLONZKA, Oleg
  • GHANI, Tahir
Agents
  • WANG, Yuke
  • AUYEUNG, Al
  • BLAIR, Steven R.
  • COFIELD, Michael A.
  • GARTHWAITE, Martin S.
  • LEE, Katherine D.
  • MAKI, Nathan R.
  • MARLINK, Jeffrey S.
  • MEININGER, Mark M.
  • MOORE, Michael S.
  • PARKER, Wesley E.
  • RASKIN, Vladimir
  • STRAUSS, Ryan N.
  • DANSKIN, Timothy A.
Priority Data
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) PROTECTION LAYERS FOR MAGNETIC TUNNEL JUNCTIONS
(FR) COUCHES DE PROTECTION POUR JONCTIONS TUNNEL MAGNÉTIQUES
Abstract
(EN)
Embodiments herein describe techniques for a semiconductor device, which includes a bottom electrode, and a MTJ pillar above the bottom electrode, where the MTJ pillar includes a MTJ stack having a free layer and a reference layer, and a top electrode above the MTJ stack. A portion of a surface of the bottom electrode does not overlap with the MTJ pillar. The device may further include a hermetic dielectric capping layer that conformally covers the MTJ pillar and the portion of the surface of the bottom electrode. The hermetic dielectric capping layer may be a protection layer formed at lower temperatures without adversely impacting the performance of the protected MTJ stack. Other embodiments may be described and/or claimed.
(FR)
Des modes de réalisation de la présente invention décrivent des techniques pour un dispositif à semiconducteur, qui comprend une électrode inférieure, et un pilier MTJ au-dessus de l'électrode inférieure, le pilier MTJ comprenant un empilement MTJ ayant une couche libre et une couche de référence, et une électrode supérieure au-dessus de l'empilement MTJ. Une partie d'une surface de l'électrode inférieure ne chevauche pas le pilier MTJ. Le dispositif peut en outre comprendre une couche de recouvrement diélectrique hermétique qui recouvre de manière conforme le pilier MTJ et la partie de la surface de l'électrode inférieure. La couche de recouvrement diélectrique hermétique peut être une couche de protection formée à des températures inférieures sans affecter négativement les performances de l'empilement MTJ protégé. D'autres modes de réalisation peuvent être décrits et/ou revendiqués.
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