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1. WO2018125135 - SRAM WITH HIERARCHICAL BIT LINES IN MONOLITHIC 3D INTEGRATED CHIPS

Publication Number WO/2018/125135
Publication Date 05.07.2018
International Application No. PCT/US2016/069188
International Filing Date 29.12.2016
IPC
G11C 11/413 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
G11C 11/419 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
417for memory cells of the field-effect type
419Read-write circuits
G11C 7/06 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
06Sense amplifiers; Associated circuits
G11C 7/12 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
12Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
CPC
G11C 11/412
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming ; static; cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
412using field-effect transistors only
G11C 11/417
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming ; static; cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction
417for memory cells of the field-effect type
G11C 11/419
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming ; static; cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction
417for memory cells of the field-effect type
419Read-write [R-W] circuits
G11C 2207/002
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
2207Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
002Isolation gates, i.e. gates coupling bit lines to the sense amplifier
G11C 2207/005
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
2207Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
005Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
G11C 7/18
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
18Bit line organisation; Bit line lay-out
Applicants
  • INTEL CORPORATION [US]/[US]
Inventors
  • WANG, Yih
Agents
  • WEISKOPF, Marie A.
Priority Data
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SRAM WITH HIERARCHICAL BIT LINES IN MONOLITHIC 3D INTEGRATED CHIPS
(FR) SRAM AVEC LIGNES DE BITS HIÉRARCHIQUES DANS DES PUCES INTÉGRÉES 3D MONOLITHIQUES
Abstract
(EN)
A memory device includes a first plurality of memory cells, a second plurality of memory cells, and a local sense amplifier between the first plurality of memory cells and the second plurality of memory cells, all on a first level, and a local bit line on a second level. The second level is vertically separated by one or more first inter-level dielectric layers from the first level in a first direction and the local bit line is electrically coupled to each memory cell of the first plurality of memory cells and the second plurality of memory cells, as well as the local sense amplifier. The memory device also includes a global bit line on a third level vertically separated by one or more inter-level dielectric layers from the first level in a second direction opposite the first direction, with the global bit line electrically coupled to the local sense amplifier.
(FR)
L'invention concerne un dispositif de mémoire comprenant une première pluralité de cellules de mémoire, une seconde pluralité de cellules de mémoire, et un amplificateur de détection local entre la première pluralité de cellules de mémoire et la seconde pluralité de cellules de mémoire, tous sur un premier niveau, et une ligne de bits locale sur un second niveau. Le second niveau est séparé verticalement par une ou plusieurs premières couches diélectriques inter-niveaux à partir du premier niveau dans une première direction et la ligne de bits locale est électriquement couplée à chaque cellule de mémoire de la première pluralité de cellules de mémoire et de la seconde pluralité de cellules de mémoire, ainsi que l'amplificateur de détection local. Le dispositif de mémoire comprend également une ligne de bits globale sur un troisième niveau séparé verticalement par une ou plusieurs couches diélectriques inter-niveaux à partir du premier niveau dans une seconde direction opposée à la première direction, la ligne de bits globale étant électriquement couplée à l'amplificateur de détection local.
Also published as
Latest bibliographic data on file with the International Bureau