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1. (WO2018125127) METHODS OF FORMING THIN FILM RESISTOR STRUCTURES UTILIZING INTERCONNECT LINER MATERIALS

Pub. No.:    WO/2018/125127    International Application No.:    PCT/US2016/069153
Publication Date: Fri Jul 06 01:59:59 CEST 2018 International Filing Date: Fri Dec 30 00:59:59 CET 2016
IPC: H01L 21/768
Applicants: INTEL CORPORATION
Inventors: LIN, Kevin
JEZEWSKI, Christopher J.
VREELAND, Richard F.
TRONIC, Tristan A.
Title: METHODS OF FORMING THIN FILM RESISTOR STRUCTURES UTILIZING INTERCONNECT LINER MATERIALS
Abstract:
Methods/structures of forming thin film resistors using interconnect liner materials are described. Those methods/structures may include forming a first liner in a first trench, wherein the first trench is disposed in a dielectric layer that is disposed on a substrate. Forming a second liner in a second trench, wherein the second trench is adjacent the first trench, forming an interconnect material on the first liner in the first trench, adjusting a resistance value of the second liner, forming a first contact structure on a top surface of the interconnect material, and forming a second contact structure on the second liner.