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1. WO2018125122 - FERROELECTRIC FIELD-EFFECT TRANSISTOR DEVICES HAVING A TOP GATE AND A BOTTOM GATE

Publication Number WO/2018/125122
Publication Date 05.07.2018
International Application No. PCT/US2016/069139
International Filing Date 29.12.2016
IPC
H01L 29/78 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
78with field effect produced by an insulated gate
H01L 29/66 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
H01L 29/51 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40Electrodes
43characterised by the materials of which they are formed
49Metal-insulator semiconductor electrodes
51Insulating materials associated therewith
H01L 27/11585 2017.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11585with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor or metal-ferroelectric-metal-insulator-semiconductor
CPC
G11C 5/063
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
06Arrangements for interconnecting storage elements electrically, e.g. by wiring
063Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
H01L 27/1159
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11585with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS]
1159characterised by the memory core region
H01L 29/40111
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
401Multistep manufacturing processes
4011for data storage electrodes
40111the electrodes comprising a layer which is used for its ferroelectric properties
H01L 29/516
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
43characterised by the materials of which they are formed
49Metal-insulator-semiconductor electrodes, ; e.g. gates of MOSFET
51Insulating materials associated therewith
516with at least one ferroelectric layer
H01L 29/6684
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
66007Multistep manufacturing processes
66075of devices having semiconductor bodies comprising group 14 or group 13/15 materials
66227the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
66409Unipolar field-effect transistors
66477with an insulated gate, i.e. MISFET
6684with a ferroelectric gate insulator
H01L 29/78391
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
76Unipolar devices ; , e.g. field effect transistors
772Field effect transistors
78with field effect produced by an insulated gate
78391the gate comprising a layer which is used for its ferroelectric properties
Applicants
  • INTEL CORPORATION [US]/[US]
Inventors
  • DOYLE, Brian S.
  • OGUZ, Kaan
  • TSENG, Ricky J.
  • O'BRIEN, Kevin P.
Agents
  • CHRISTON, Rebecca C.
Priority Data
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) FERROELECTRIC FIELD-EFFECT TRANSISTOR DEVICES HAVING A TOP GATE AND A BOTTOM GATE
(FR) DISPOSITIFS À TRANSISTORS À EFFET DE CHAMP FERROÉLECTRIQUES AYANT UNE GRILLE SUPÉRIEURE ET UNE GRILLE INFÉRIEURE
Abstract
(EN)
Techniques are disclosed for forming integrated circuit (IC) devices that include ferroelectric field-effect transistors (FE-FETs) having a top gate and a bottom gate (or, generally, a dual-gate configuration). The disclosed FE-FET devices may be formed in the back end of the IC structure and may be implemented with various materials that exhibit ferroelectric properties when processed at temperatures within the thermal budget of the back-end processing. The disclosed back-end FE-FET devices can achieve greater than two resistance states, depending on the direction of poling of the top and bottom gates, thereby enabling the formation of 3-state and 4-state memory devices, for example. Additionally, as will be appreciated in light of this disclosure, the disclosed back-end FE-FET devices can free up floor space in the front-end, thereby providing space for additional devices in the front-end.
(FR)
L'invention concerne des techniques de formation de dispositifs à circuit intégré (IC) qui comprennent des transistors à effet de champ ferroélectriques (FE-FET) ayant une grille supérieure et une grille inférieure (ou, généralement, une configuration à double grille) Les dispositifs FE-FET décrits peuvent être formés dans l'extrémité arrière de la structure CI et peuvent être mis en œuvre avec divers matériaux qui présentent des propriétés ferroélectriques lorsqu'ils sont traités à des températures dans le budget thermique du traitement dorsal. Les dispositifs FE-FET à extrémité arrière décrits peuvent atteindre plus de deux états de résistance, en fonction de la direction de polarisation des grilles supérieure et inférieure, permettant ainsi la formation de dispositifs de mémoire à 3 états et à 4 états, par exemple. De plus, comme il sera apprécié à la lumière de la présente invention, les dispositifs FE-FET à extrémité arrière décrits peuvent libérer un espace utile dans l'extrémité avant, fournissant ainsi un espace pour des dispositifs supplémentaires dans l'extrémité avant.
Also published as
Latest bibliographic data on file with the International Bureau