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1. (WO2018125120) TECHNIQUES FOR FORMING DUAL-STRAIN FINS FOR CO-INTEGRATED N-MOS AND P-MOS DEVICES
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Pub. No.: WO/2018/125120 International Application No.: PCT/US2016/069126
Publication Date: 05.07.2018 International Filing Date: 29.12.2016
IPC:
H01L 29/78 (2006.01) ,H01L 29/66 (2006.01) ,H01L 29/417 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
417
carrying the current to be rectified, amplified or switched
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
CEA, Stephen M.; US
MEHANDRU, Rishabh; US
BOWONDER, Anupama; US
MURTHY, Anand S.; US
GHANI, Tahir; US
Agent:
BRODSKY, Stephen I.; US
Priority Data:
Title (EN) TECHNIQUES FOR FORMING DUAL-STRAIN FINS FOR CO-INTEGRATED N-MOS AND P-MOS DEVICES
(FR) TECHNIQUES DE FORMATION D'AILETTES À DOUBLE EFFORT POUR DISPOSITIFS N-MOS ET P-MOS COINTÉGRÉS
Abstract:
(EN) Techniques are disclosed for forming dual-strain fins for co-integrated n-MOS and p-MOS devices. The techniques can be used to monolithically form tensile-strained fins to be used for n-MOS devices and compressive-strained fins to be used for p-MOS devices utilizing the same substrate, such that a single integrated circuit (IC) can include both of the devices. In some instances, the oppositely stressed fins may be achieved by employing a relaxed SiGe (rSiGe) layer from which the tensile and compressive-strained material can be formed. In some instances, the techniques include the formation of tensile-stressed Si and/or SiGe fins and compressive-stressed SiGe and/or Ge fins using a single relaxed SiGe layer to enable the co-integration of n-MOS and p-MOS devices, where each set of devices includes preferred materials and preferred stress/strain to enhance their respective performance. In some cases, improvements of at least 25% in drive current can be obtained.
(FR) L'invention concerne des techniques de formation d'ailettes à double effort pour des dispositifs N-MOS et P-MOS cointégrés. Les techniques peuvent être utilisées pour former de façon monolithique des ailettes soumises à un effort de traction destinées à être utilisées pour des dispositifs N-MOS et des ailettes soumises à un effort de compression destinées à être utilisées pour des dispositifs P-MOS utilisant le même substrat, de sorte qu'un seul circuit intégré (IC) peut inclure les deux dispositifs. Dans certains cas, les ailettes soumises à des contraintes opposées peuvent être obtenues en utilisant une couche de SiGe soulagée (rSiGe) à partir de laquelle peut être formé le matériau soumis à un effort de traction et de compression. Dans certains cas, les techniques comprennent la formation d'ailettes en Si et/ou en SiGe soumises à une contrainte de traction et d'ailettes en SiGe et/ou en Ge soumises à une contrainte de compression en utilisant une seule couche de SiGe soulagée pour permettre la cointégration de dispositifs N-MOS et P-MOS. Chaque ensemble de dispositifs comprend des matériaux préférés et une contrainte/un effort préféré(e) pour améliorer leurs performances respectives. Dans certains cas, des améliorations d'au moins 25 % dans un courant d'attaque peuvent être obtenues.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)