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1. (WO2018125113) PHOTONIC ENGINE PLATFORM UTILIZING EMBEDDED WAFER LEVEL PACKAGING INTEGRATION
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/125113 International Application No.: PCT/US2016/069095
Publication Date: 05.07.2018 International Filing Date: 29.12.2016
IPC:
H01L 25/16 (2006.01) ,H01L 25/00 (2006.01) ,H01L 25/18 (2006.01) ,H01L 23/00 (2006.01) ,H01L 23/498 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
16
the devices being of types provided for in two or more different main groups of groups H01L27/-H01L51/139
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18
the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
498
Leads on insulating substrates
Applicants: INTEL CORPORATION[US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors: YIM, Myung Jin; US
KIM, Sang Yup; US
Agent: ORTIZ, Kathy J.; US
Priority Data:
Title (EN) PHOTONIC ENGINE PLATFORM UTILIZING EMBEDDED WAFER LEVEL PACKAGING INTEGRATION
(FR) PLATE-FORME DE MOTEUR PHOTONIQUE METTANT EN ŒUVRE UNE INTÉGRATION DE BOÎTIERS ENCASTRÉS NIVEAU TRANCHE
Abstract:
(EN) Methods/structures of forming package structures are described. Those methods/structures may include a mold material, wherein a plurality of die are embedded in the mold material, a package substrate, wherein the mold material comprising the plurality of die is at least partially embedded in a cavity of the substrate, and wherein a liner is between side and bottom portions of the mold material and the package substrate, at least one optical die disposed on the package substrate, and a thermal solution disposed on a top surface of the optical die.
(FR) La présente invention concerne des procédés/structures de formation de structures d'encapsulation. Ces procédés/structures peuvent comprendre un matériau de moule, une pluralité de puces étant encastrées dans le matériau de moule, un substrat de boîtier, le matériau de moule comprenant la pluralité de puces étant au moins partiellement encastré dans une cavité du substrat, et un revêtement étant disposé entre des parties latérales et inférieures du matériau de moule et le substrat de boîtier, au moins une puce optique disposée sur le substrat de boîtier, et une solution thermique disposée sur une surface supérieure de la puce optique.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)