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1. (WO2018125109) SUBTRACTIVE PLUG ETCHING

Pub. No.:    WO/2018/125109    International Application No.:    PCT/US2016/069083
Publication Date: Fri Jul 06 01:59:59 CEST 2018 International Filing Date: Fri Dec 30 00:59:59 CET 2016
IPC: H01L 21/768
Applicants: INTEL CORPORATION
Inventors: LIN, Kevin
BRISTOL, Robert L.
CHANDHOK, Manish
Title: SUBTRACTIVE PLUG ETCHING
Abstract:
In an example, there is disclosed a method of manufacturing an integrated circuit, including: depositing a metal interconnect layer on an interlayer dielectric (ILD) including an ILD material, including a first interconnect and a second interconnect; depositing a first cross grating having a first dielectric material; depositing a second cross grating having a second dielectric material, the second cross grating substantially perpendicular to the first cross grating; subtractively etching a plug pattern between the first interconnect and the second interconnect; filling the plug pattern with a plug dielectric material; and depositing a via to electrically couple the second interconnect to a different layer.