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1. (WO2018125081) TRANSISTORS EMPLOYING BLANKET-GROWN METAMORPHIC BUFFER LAYER
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Pub. No.: WO/2018/125081 International Application No.: PCT/US2016/068885
Publication Date: 05.07.2018 International Filing Date: 28.12.2016
IPC:
H01L 29/78 (2006.01) ,H01L 29/66 (2006.01) ,H01L 29/778 (2006.01) ,H01L 29/73 (2006.01) ,H01L 29/423 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
778
with two-dimensional charge carrier gas channel, e.g. HEMT
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
70
Bipolar devices
72
Transistor-type devices, i.e. able to continuously respond to applied control signals
73
Bipolar junction transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
423
not carrying the current to be rectified, amplified or switched
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
RACHMADY, Willy; US
MURTHY, Anand S.; US
METZ, Matthew V.; US
MINUTILLO, Nicholas G.; US
MA, Sean T.; US
DEWEY, Gilbert; US
KAVALIEROS, Jack T.; US
GHANI, Tahir; US
Agent:
BRODSKY, Stephen I.; US
Priority Data:
Title (EN) TRANSISTORS EMPLOYING BLANKET-GROWN METAMORPHIC BUFFER LAYER
(FR) TRANSISTORS UTILISANT UNE COUCHE TAMPON MÉTAMORPHIQUE À CROISSANCE DE COUVERTURE
Abstract:
(EN) Techniques are disclosed for forming transistors employing a blanket-grown metamorphic buffer layer. As can be understood based on this disclosure, employing the buffer layer enables the integration of relatively high-quality (or device-quality) epitaxial semiconductor material with a substrate that it could not otherwise be integrated with due to a lattice mismatch. To provide an example, the techniques can enable the monolithic formation of relatively high-quality InGaAs for highly scaled InGaAs transistors above a Si substrate by employing an intervening InAlAs metamorphic buffer layer. Note that metamorphic designates that the layer has been grown beyond its strain relaxation critical thickness. Achieving a metamorphic thickness for the buffer layer allows the lattice mismatch that would otherwise be present between the epitaxial semiconductor material and the substrate material to be mitigated. In some cases, the buffer layer also provides electrical isolation for the overlying epitaxial semiconductor material.
(FR) L'invention concerne des techniques de formation de transistors utilisant une couche tampon métamorphique à croissance de couverture. Comme on peut le comprendre sur la base de la présente invention, l'utilisation de la couche tampon permet l'intégration d'un matériau semi-conducteur épitaxial de qualité relativement élevée (ou de qualité dispositif) à un substrat, que l'on ne pourrait autrement pas intégrer du fait d'un désaccord de réseau. À titre d'exemple, les techniques peuvent permettre la formation monolithique d'InGaAs de qualité relativement élevée pour des transistors à InGaAs à grande échelle au-dessus d'un substrat en Si par l'utilisation d'une couche tampon d'InAlAs métamorphique d'intervention. À noter que le terme métamorphique indique que la couche a crû au-delà de son épaisseur critique de relaxation de contrainte. L'obtention d'une épaisseur métamorphique de la couche tampon permet d'atténuer le désaccord de réseau qui serait autrement présent entre le matériau semi-conducteur épitaxial et le matériau de substrat. Dans certains cas, la couche tampon fournit également une isolation électrique du matériau semi-conducteur épitaxial sus-jacent.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)