Asymmetric transistors and related methods and devices are disclosed. A transistor includes a semiconductor material doped with a first type of charge carriers along the gate oxide according to an asymmetric doping profile with a halo region on a source side. The transistor also includes a source including a lightly doped drain (LDD) on the source side, and a drain having a doping profile of charge carriers of a second type graded in a decreasing manner toward the source side. A method includes applying a large angle tilt implant drain (LATID) process to a drain side, a halo implant process to a source side, and applying an LDD process on the source side. A memory device includes an asymmetric transistor. A computing device includes an asymmetric transistor.