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1. (WO2018125066) PACKAGE SUBSTRATE HAVING COPPER ALLOY SPUTTER SEED LAYER AND HIGH DENSITY INTERCONNECTS
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Pub. No.: WO/2018/125066 International Application No.: PCT/US2016/068773
Publication Date: 05.07.2018 International Filing Date: 28.12.2016
IPC:
H01L 23/498 (2006.01) ,H01L 23/12 (2006.01) ,H05K 3/38 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
498
Leads on insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
38
Improvement of the adhesion between the insulating substrate and the metal
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054-1549, US
Inventors:
MAY, Robert Alan; US
DARMAWIKARTA, Kristof Kuwawi; US
BOYAPATI, Sri Ranga Sai; US
GAAN, Sandeep; US
PIETAMBARAM, Srinivas V.; US
Agent:
MASSIE FEUSTEL, Alisha; US
Priority Data:
Title (EN) PACKAGE SUBSTRATE HAVING COPPER ALLOY SPUTTER SEED LAYER AND HIGH DENSITY INTERCONNECTS
(FR) SUBSTRAT DE BOÎTIER AYANT UNE COUCHE DE GERME DE PULVÉRISATION EN ALLIAGE DE CUIVRE ET DES INTERCONNEXIONS HAUTE DENSITÉ
Abstract:
(EN) Integrated circuit (IC) package substrates having high density interconnects with a sputter seed layer containing a copper alloy, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, a package substrate may include a first dielectric layer, a sputter seed layer disposed on the first dielectric layer, wherein the seed layer includes a copper alloy, a patterned conductive layer disposed on the seed layer, and a second dielectric layer over the patterned conductive layer.
(FR) L'invention concerne des substrats de boîtier de circuit intégré (IC) ayant des interconnexions haute densité avec une couche de germe de pulvérisation contenant un alliage de cuivre, ainsi que des structures, des dispositifs et des procédés associés. Par exemple, dans certains modes de réalisation, un substrat de boîtier peut comprendre une première couche diélectrique, une couche de germe de pulvérisation disposée sur la première couche diélectrique, la couche de germe comprenant un alliage de cuivre, une couche conductrice à motifs disposée sur la couche de germe, et une seconde couche diélectrique sur la couche conductrice à motifs.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)