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1. (WO2018125064) DEEPLY SCALED METAL INTERCONNECTS WITH HIGH ASPECT RATIO

Pub. No.:    WO/2018/125064    International Application No.:    PCT/US2016/068763
Publication Date: Fri Jul 06 01:59:59 CEST 2018 International Filing Date: Wed Dec 28 00:59:59 CET 2016
IPC: H01L 21/768
Applicants: INTEL CORPORATION
Inventors: LIU, En-Shao
CASSIDY-COMFORT, Everett S.
PARK, Joodong
LEE, Chen-Guan
HAFEZ, Walid M.
JAN, Chia-Hong
Title: DEEPLY SCALED METAL INTERCONNECTS WITH HIGH ASPECT RATIO
Abstract:
Embodiments of the present disclosure describe techniques and configurations associated with an integrated circuit (IC) structure including an interconnect layer. Semiconductor fins may be formed on an underlying layer. A first dielectric material may be formed on the sidewalls of the semiconductor fins, and a second dielectric material may be formed between the semiconductor fins and the portions of the first dielectric material. The semiconductor fins may be removed and replaced with a metal to form respective interconnects. The first dielectric material may serve as an etch stop layer for removal of the semiconductor fins. The second dielectric material may have a lower dielectric constant than the first dielectric material to reduce capacitance between the interconnects. Other embodiments may be described and/or claimed.