WIPO logo
Mobile | Deutsch | Español | Français | 日本語 | 한국어 | Português | Русский | 中文 | العربية |
PATENTSCOPE

Search International and National Patent Collections
World Intellectual Property Organization
Options
Query Language
Stem
Sort by:
List Length
1. (WO2018125060) HIGH DENSITY METAL-INSULATOR-METAL DECOUPLING CAPACITOR
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/125060 International Application No.: PCT/US2016/068753
Publication Date: 05.07.2018 International Filing Date: 27.12.2016
IPC:
H01L 27/108 (2006.01) ,H01L 49/02 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
108
Dynamic random access memory structures
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
49
Solid state devices not provided for in groups H01L27/-H01L47/99; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
02
Thin-film or thick-film devices
Applicants: INTEL CORPORATION[US/US]; 2200 Mission College Blvd. Santa Clara, CA 95054, US
Inventors: WANG, Yih; US
Agent: BRASK, Justin, K.; US
Priority Data:
Title (EN) HIGH DENSITY METAL-INSULATOR-METAL DECOUPLING CAPACITOR
(FR) CONDENSATEUR DE DÉCOUPLAGE MÉTAL-ISOLANT-MÉTAL À HAUTE DENSITÉ
Abstract:
(EN) An apparatus comprises one or more logic circuit blocks coupled between a supply voltage and ground and a decoupling capacitor coupled between the supply voltage and ground in parallel to the one or more logic circuit blocks, comprising a first high-density three-dimensional (3D) metal-insulator-metal (MIM) trench capacitor coupled in series with a second high-density 3D MIM trench capacitor.
(FR) L’invention concerne un appareil qui comprend un ou plusieurs blocs de circuit logique couplés entre une tension d'alimentation et une masse et un condensateur de découplage couplé entre la tension d'alimentation et la masse en parallèle avec le ou les blocs de circuit logique, comprenant un premier condensateur en tranchée métal-isolant-métal (MIM) tridimensionnel (3D) haute densité couplé en série avec un second condensateur en tranchée MIM 3D haute densité.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)