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1. (WO2018125055) PACKAGES OF STACKING INTEGRATED CIRCUITS

Pub. No.:    WO/2018/125055    International Application No.:    PCT/US2016/068742
Publication Date: Fri Jul 06 01:59:59 CEST 2018 International Filing Date: Wed Dec 28 00:59:59 CET 2016
IPC: H01L 23/48
H01L 21/768
H01L 23/00
H01L 23/498
H01L 23/538
H01L 23/532
Applicants: INTEL IP CORPORATION
Inventors: REINGRUBER, Klaus
SEIDEMANN, Georg
WOLTER, Andreas
WAIDHAS, Bernd
WAGNER, Thomas
Title: PACKAGES OF STACKING INTEGRATED CIRCUITS
Abstract:
Embodiments may include an IC having an active substrate containing devices, and a bulk substrate, separated by an oxide layer or an etching stop layer. The IC may be partially thinned from a backside of the bulk substrate to create a cavity, while maintaining the dicing streets and/or the edges of the bulk substrate without being thinned. The cavity may be surrounded by a first edge and a second edge of the bulk substrate. An additional IC may be placed within the cavity of the bulk substrate to form a stacking IC with a reduced height. The ICs of the stacking IC may be electronically coupled using TSVs embedded within the active substrate of the ICs. Other embodiments may be described and/or claimed.