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1. (WO2018125046) DIVIDER-LESS FRACTIONAL PLL ARCHITECTURE

Pub. No.:    WO/2018/125046    International Application No.:    PCT/US2016/068696
Publication Date: Fri Jul 06 01:59:59 CEST 2018 International Filing Date: Wed Dec 28 00:59:59 CET 2016
IPC: H03L 7/089
H03L 7/099
G04F 10/00
H03L 7/093
Applicants: INTEL CORPORATION
NASSAR, Elias
FAYNEH, Eyal
FALKOV, Inbar
BANIN, Elan
BANIN, Rotem
DEGANI, Ofir
NASSAR, Samer
Inventors: NASSAR, Elias
FAYNEH, Eyal
FALKOV, Inbar
BANIN, Elan
BANIN, Rotem
DEGANI, Ofir
NASSAR, Samer
Title: DIVIDER-LESS FRACTIONAL PLL ARCHITECTURE
Abstract:
A divider-less fractional digital phase locked loop (PLL) is disclosed and can include a time-to-digital converter (TDC) to receive a reference clock signal and a digitally control oscillator (DCO) clock signal, and generate a phase difference signal based on the reference clock signal and the DCO clock signal. A counter coupled in parallel to the TDC can receive the clock signal and count an output frequency of the clock signal to detect reference noise within the reference signal that is above a threshold. A sampler can sample an output of the counter using a replica of the reference signal, and generate a plurality of samples. A sample selector can select one of the plurality of samples based on the phase difference signal. A digital phase detector (DPD) can generate an output phase measurement based on the phase difference signal and the selected sample of the plurality of samples.