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1. (WO2018125045) TARGETED BURN-IN ON AN INTEGRATED CIRCUIT

Pub. No.:    WO/2018/125045    International Application No.:    PCT/US2016/068690
Publication Date: Fri Jul 06 01:59:59 CEST 2018 International Filing Date: Wed Dec 28 00:59:59 CET 2016
IPC: G01R 31/28
Applicants: INTEL CORPORATION
Inventors: SINGH, Dhruv
RAJAPAKSA, Indrajith
SONG, Junho
Title: TARGETED BURN-IN ON AN INTEGRATED CIRCUIT
Abstract:
Embodiments of the present disclosure describe techniques for a diode array layout in an integrated circuit. An IC (integrated circuit) may include a substrate; circuitry formed above the substrate; resistors coupled to respective different regions of the circuitry; and selection circuitry to select a resistor of the resistors to receive a current to cause the selected resistor to heat a corresponding region of the regions to a predetermined burn-in temperature.