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1. (WO2018125035) TRANSISTORS INCLUDING FINAL SOURCE/DRAIN MATERIAL PROCESSED AFTER REPLACEMENT GATE PROCESSING

Pub. No.:    WO/2018/125035    International Application No.:    PCT/US2016/068660
Publication Date: Fri Jul 06 01:59:59 CEST 2018 International Filing Date: Wed Dec 28 00:59:59 CET 2016
IPC: H01L 29/78
H01L 29/66
H01L 21/8238
H01L 29/423
Applicants: INTEL CORPORATION
Inventors: JAMBUNATHAN, Karthik
MADDOX, Scott J.
MURTHY, Anand S.
GLASS, Glenn A.
MEHANDRU, Rishabh
WEBER, Cory E.
GHANI, Tahir
Title: TRANSISTORS INCLUDING FINAL SOURCE/DRAIN MATERIAL PROCESSED AFTER REPLACEMENT GATE PROCESSING
Abstract:
Techniques are disclosed for forming transistors including final source/drain (S/D) material processed after replacement gate processing. In some cases, at least one of the S/D regions of a transistor may initially be formed with sacrificial S/D material that is intended to be removed and replaced later in the process flow with final S/D material. The sacrificial S/D material may be formed during the typical S/D region formation (e.g., after the dummy gate stack and gate spacers have been formed). Then, the sacrificial S/D material may be removed and replaced with final S/D material through a corresponding S/D contact trench, such that the final S/D material is not formed until near the end of the front-end-of line (FEOL) processing. This allows delaying formation of the final S/D material until after replacement gate processing has occurred, thereby addressing the problem of dopant diffusion from the S/D regions into the channel.