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1. (WO2018124506) PHASE LOCKED LOOP USING DIRECT DIGITAL FREQUENCY SYNTHESIZER

Pub. No.:    WO/2018/124506    International Application No.:    PCT/KR2017/013868
Publication Date: Fri Jul 06 01:59:59 CEST 2018 International Filing Date: Fri Dec 01 00:59:59 CET 2017
IPC: H03L 7/197
H03L 7/083
G06F 1/03
H03L 7/081
H03L 7/093
Applicants: POSTECH ACADEMY-INDUSTRY FOUNDATION
포항공과대학교 산학협력단
Inventors: SIM, Jae Yoon
심재윤
CHO, Hwa Suk
조화숙
Title: PHASE LOCKED LOOP USING DIRECT DIGITAL FREQUENCY SYNTHESIZER
Abstract:
The present invention relates to a design technique for a phase locked loop (PLL) that produces an accurate clock frequency in a clock synchronization system. The present invention proposes a hardware description language (HDL)-based new structure to reduce a chip area of a frequency synthesizer and secure a wide frequency operating range. Further, the present invention allows the entire circuit of the frequency synthesizer to be all-synthesizable by using only a hardware description language, and enables an automatic layout (auto P&R) through a tool, so as to reduce a design cost of a designer.