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|1. (WO2018124506) PHASE LOCKED LOOP USING DIRECT DIGITAL FREQUENCY SYNTHESIZER|
|Applicants:||POSTECH ACADEMY-INDUSTRY FOUNDATION
|Inventors:||SIM, Jae Yoon
CHO, Hwa Suk
|Title:||PHASE LOCKED LOOP USING DIRECT DIGITAL FREQUENCY SYNTHESIZER|
The present invention relates to a design technique for a phase locked loop (PLL) that produces an accurate clock frequency in a clock synchronization system. The present invention proposes a hardware description language (HDL)-based new structure to reduce a chip area of a frequency synthesizer and secure a wide frequency operating range. Further, the present invention allows the entire circuit of the frequency synthesizer to be all-synthesizable by using only a hardware description language, and enables an automatic layout (auto P&R) through a tool, so as to reduce a design cost of a designer.