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1. (WO2018124506) PHASE LOCKED LOOP USING DIRECT DIGITAL FREQUENCY SYNTHESIZER
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Pub. No.: WO/2018/124506 International Application No.: PCT/KR2017/013868
Publication Date: 05.07.2018 International Filing Date: 30.11.2017
IPC:
H03L 7/197 (2006.01) ,H03L 7/083 (2006.01) ,G06F 1/03 (2006.01) ,H03L 7/081 (2006.01) ,H03L 7/093 (2006.01)
Applicants: POSTECH ACADEMY-INDUSTRY FOUNDATION[KR/KR]; 77, Cheongam-ro, Nam-gu Pohang-si Gyeongsangbuk-do 37673, KR
Inventors: SIM, Jae Yoon; KR
CHO, Hwa Suk; KR
Agent: LEE, Cheol Hee; KR
Priority Data:
10-2016-018293829.12.2016KR
Title (EN) PHASE LOCKED LOOP USING DIRECT DIGITAL FREQUENCY SYNTHESIZER
(FR) BOUCLE À VERROUILLAGE DE PHASE UTILISANT UN SYNTHÉTISEUR NUMÉRIQUE DIRECT DE FRÉQUENCES
(KO) 직접 디지털 주파수 합성기를 이용한 위상 고정루프
Abstract: front page image
(EN) The present invention relates to a design technique for a phase locked loop (PLL) that produces an accurate clock frequency in a clock synchronization system. The present invention proposes a hardware description language (HDL)-based new structure to reduce a chip area of a frequency synthesizer and secure a wide frequency operating range. Further, the present invention allows the entire circuit of the frequency synthesizer to be all-synthesizable by using only a hardware description language, and enables an automatic layout (auto P&R) through a tool, so as to reduce a design cost of a designer.
(FR) La présente invention concerne une technique de conception destinée à une boucle à verrouillage de phase (PLL) qui produit une fréquence d'horloge précise dans un système de synchronisation d'horloge. La présente invention propose une nouvelle structure basée sur langage de description de matériel (HDL) permettant de réduire une zone de puce d'un synthétiseur de fréquences et de sécuriser une plage de fonctionnement à large bande. En outre, la présente invention permet à l'ensemble du circuit du synthétiseur de fréquences d'être entièrement synthétisé à l'aide uniquement d'un langage de description de matériel, et permet une mise en page automatique (P&R automatique) par l'intermédiaire d'un outil, de façon à réduire un coût de conception d'un concepteur.
(KO) 본 발명은, 본 발명은, 클럭 동기 시스템에서 정확한 클럭 주파수를 만들어 내는 위상고정루프(PLL)의 설계 기술에 관한 발명이다. 이러한 본 발명은, 하드웨어 기술 언어(HDL) 기반의 새로운 구조를 제안하여 주파수 합성기의 칩 면적이 줄어들고 넓은 주파수 동작 범위가 확보되도록 하였다. 또한, 하드웨어 기술 언어 만을 사용하여 주파수 합성기 전체 회로가 합성 가능(all-synthesizable)해지고, 툴을 통한 자동 레이아웃(auto P&R)이 가능해져 설계자의 디자인 설계 비용(design cost)이 감소되는 효과가 있다.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Korean (KO)
Filing Language: Korean (KO)