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1. (WO2018123823) MANUFACTURING METHOD FOR COLUMNAR SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2018/123823 International Application No.: PCT/JP2017/046000
Publication Date: 05.07.2018 International Filing Date: 21.12.2017
IPC:
H01L 21/8244 (2006.01) ,H01L 27/11 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8239
Memory structures
8244
Static random access memory structures (SRAM)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
11
Static random access memory structures
Applicants:
ユニサンティス エレクトロニクス シンガポール プライベート リミテッド UNISANTIS ELECTRONICS SINGAPORE PTE. LTD. [SG/SG]; ノースブリッジロード 111、ペニンシュラ プラザ #16-04 111, North Bridge Road, #16-04, Peninsula Plaza 179098, SG (AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BE, BF, BG, BH, BJ, BN, BR, BW, BY, BZ, CA, CF, CG, CH, CI, CL, CM, CN, CO, CR, CU, CY, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, FR, GA, GB, GD, GE, GH, GM, GN, GQ, GR, GT, GW, HN, HR, HU, ID, IE, IL, IN, IR, IS, IT, JO, JP, KE, KG, KH, KM, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MC, MD, ME, MG, MK, ML, MN, MR, MT, MW, MX, MY, MZ, NA, NE, NG, NI, NL, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SI, SK, SL, SM, SN, ST, SV, SY, SZ, TD, TG, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, UZ, VC, VN, ZA, ZM, ZW)
舛岡 富士雄 MASUOKA Fujio [JP/JP]; JP (US)
原田 望 HARADA Nozomu [JP/JP]; JP (US)
中村 広記 NAKAMURA Hiroki [JP/JP]; JP (US)
マタニア フィリップ MATAGNE Phillipe [BE/BE]; BE (US)
菊池 善明 KIKUCHI Yoshiaki [JP/BE]; BE (US)
Inventors:
舛岡 富士雄 MASUOKA Fujio; JP
原田 望 HARADA Nozomu; JP
中村 広記 NAKAMURA Hiroki; JP
マタニア フィリップ MATAGNE Phillipe; BE
菊池 善明 KIKUCHI Yoshiaki; BE
Agent:
田中 伸一郎 TANAKA Shinichiro; JP
弟子丸 健 DESHIMARU Takeshi; JP
▲吉▼田 和彦 YOSHIDA Kazuhiko; JP
大塚 文昭 OHTSUKA Fumiaki; JP
西島 孝喜 NISHIJIMA Takaki; JP
須田 洋之 SUDA Hiroyuki; JP
上杉 浩 UESUGI Hiroshi; JP
近藤 直樹 KONDO Naoki; JP
Priority Data:
PCT/JP2016/08912928.12.2016JP
Title (EN) MANUFACTURING METHOD FOR COLUMNAR SEMICONDUCTOR DEVICE
(FR) PROCÉDÉ DE FABRICATION D'UN DISPOSITIF À SEMI-CONDUCTEUR EN COLONNES
(JA) 柱状半導体装置の製造方法
Abstract:
(EN) Provided is a manufacturing method for a columnar semiconductor device, the method including a step for: forming a circular belt-shaped SiO2 layer surrounding the side faces of a P+ layer 38a and N+ layers 38b, 8c formed on a Si column 6b by epitaxial crystal growth, and an AlO layer 51 on the outer peripheral section surrounding the SiO2 layer; forming belt-shaped contact holes by etching the belt-shaped SiO2 layer with the AlO layer 51 as a mask; and forming belt-shaped W layers 52c, 52d, 52e (including buffer conductor layers) at equal widths in a plan view contacting the side faces of the tops of the P+ layer 38a and N+ layers 38b, 8c by embedding the W layers 52c, 52d, 52e into the contact holes.
(FR) L'invention concerne un procédé de fabrication d'un dispositif à semi-conducteur en colonnes, le procédé comprenant des étapes consistant à: former une couche circulaire de SiO2 en forme de ceinture entourant les faces latérales d'une couche P+ 38a et de couches N+ 38b, 8c formées sur une colonne de Si 6b par croissance épitaxiale de cristaux, et une couche d'AlO 51 sur la section périphérique extérieure entourant la couche de SiO2; former des trous de contact en forme de ceinture en gravant la couche de SiO2 en forme de ceinture, la couche d'AlO 51 servant de masque; et former des couches de W 52c, 52d, 52e en forme de ceinture (comprenant des couches conductrices tampons), de largeurs égales dans une vue en plan, en contact avec les faces latérales des parties supérieures de la couche P+ 38a et des couches N+ 38b, 8c en encastrant les couches de W 52c, 52d, 52e dans les trous de contact.
(JA) 柱状半導体装置の製造方法は、Si柱6b上にエピタキシャル結晶成長により形成されたP+層38a、N+層38b、8cの側面を囲んだ円帯状のSiO2層と、これを囲んだ外周部にAlO層51と、を形成し、このAlO層51をマスクに円帯状SiO2層をエッチングして、円帯状のコンタクトホールを形成し、このコンタクトホールにW層52c、52d、52eを埋め込むことにより、P+層38a、N+層38b、8cの頂部の側面に接して、平面視において、等幅で、円帯状のW層52c、52d、52e(バッファ導体層を含む)を形成する工程を有する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)