Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2018123799) SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/123799 International Application No.: PCT/JP2017/045908
Publication Date: 05.07.2018 International Filing Date: 21.12.2017
IPC:
H01L 29/78 (2006.01) ,H01L 21/76 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
76
Making of isolation regions between components
Applicants:
パナソニックIPマネジメント株式会社 PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD. [JP/JP]; 大阪府大阪市中央区城見2丁目1番61号 1-61, Shiromi 2-chome, Chuo-ku, Osaka-shi, Osaka 5406207, JP
Inventors:
松島 芳宏 MATSUSHIMA Yoshihiro; --
曽田 茂稔 SOTA Shigetoshi; --
安田 英司 YASUDA Eiji; --
今井 俊和 IMAI Toshikazu; --
大河 亮介 OKAWA Ryosuke; --
吉田 一磨 YOSHIDA Kazuma; --
加藤 亮 KATO Ryou; --
Agent:
鎌田 健司 KAMATA Kenji; JP
前田 浩夫 MAEDA Hiroo; JP
Priority Data:
62/43934327.12.2016US
Title (EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF SEMI-CONDUCTEUR
(JA) 半導体装置
Abstract:
(EN) A semiconductor device (1) is provided with: an N-type semiconductor substrate (32) made of silicon; an N-type low-concentration impurity layer (33) in contact with an upper surface of the semiconductor substrate (32); a metal layer (31) which is in contact with an entire lower surface of the semiconductor substrate (32) and has a thickness of not less than 20 μm; and transistors (10 and 20) formed in the low-concentration impurity layer. The semiconductor substrate (32) functions as a drain region for the transistors (10 and 20). A bi-directional path of flow between the source electrodes of the transistors (10 and 20) via the semiconductor substrate (32) on the transistor (10) side, the metal layer (31), and the semiconductor substrate (32) on the transistor (20) side constitutes a main electric current path. A thickness ratio of the metal layer (31) to a semiconductor layer including the semiconductor substrate (32) and the low-concentration impurity layer (33) is greater than 0.27. The semiconductor device (1) further includes a support body (30) made of ceramic material which is adhered to the entire lower surface of the metal layer (31) only via an adhesive layer (39).
(FR) Un dispositif à semi-conducteur est pourvu : d'un substrat semi-conducteur de type N (32) en silicium ; d'une couche d'impuretés à faible concentration de type N (33) en contact avec une surface supérieure du substrat semi-conducteur (32) ; d'une couche métallique (31) qui est en contact avec une surface inférieure entière du substrat semi-conducteur (32) et a une épaisseur qui n'est pas inférieure à 20 µm ; et des transistors (10 and 20) formés dans la couche d'impuretés à faible concentration. Le substrat semi-conducteur (32) fonctionne comme une zone de drain pour les transistors (10 et 20). Un trajet bidirectionnel d'écoulement entre les électrodes de source des transistors (10 et 20) via le substrat semi-conducteur (32) sur le côté du transistor (10), la couche métallique (31), et le substrat semi-conducteur (32) sur le côté du transistor (20) constitue un trajet de courant électrique principal. Un rapport d'épaisseur de la couche métallique (31) à une couche de semi-conducteur comprenant le substrat semi-conducteur (32) et la couche d'impuretés à faible concentration (33) est supérieur à 0,27. Le dispositif semi-conducteur (1) comprend en outre un corps de support (30) en matériau céramique qui adhère à la totalité de la surface inférieure de la couche métallique (31) uniquement via une couche adhésive (39).
(JA) 半導体装置(1)は、シリコンからなるN型の半導体基板(32)と、半導体基板(32)の上面に接するN型の低濃度不純物層(33)と、半導体基板(32)の下面全面に接する20μm以上の厚さの金属層(31)と、低濃度不純物層内に形成されたトランジスタ(10および20)とを備え、半導体基板(32)は、トランジスタ(10および20)のドレイン領域として機能し、トランジスタ(10および20)のソース電極の間を、トランジスタ(10)側の半導体基板(32)、金属層(31)、トランジスタ(20)側の半導体基板(32)を経由して流れる双方向経路を主電流経路とし、半導体基板(32)と低濃度不純物層(33)とを含む半導体層に対する金属層(31)の厚さの割合は0.27より大きく、半導体装置(1)は、さらに、金属層(31)の下面全面に、接着層(39)のみを介して接着されたセラミック材料からなる支持体(30)を有する。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)